HV4530//HV4630
Functional Block Diagram
V
SS
Polarity
Blanking
Latch Enable
Data Input
Clock
Latch
32-Bit
Shift
Register
Latch
HV
OUT
2
(Outputs 3 to 30
not shown)
Latch
HV
OUT
1
HV
OUT
31
Data Out
Latch
HV
OUT
32
Function Table
Inputs
Function
All on
All off
Invert mode
Load S/R
Load
latches
Transparent
latch mode
Data
X
X
X
H or L
X
X
L
H
CLK
X
X
X
↓
Outputs
BL
L
L
H
H
H
H
H
H
POL
L
H
L
H
H
L
H
H
Shift Reg
1 2…32
*
*
*
*…*
*…*
*…*
HV Outputs
1
2…32
ON
ON…ON
Data Out
*
*
*
*
*
*
*
*
*
LE
X
X
L
L
↑
↑
OFF OFF…OFF
*
*
*
*
OFF
ON
*…*
*…*
*…*
*…*
*…*
*…*
H or L *…*
*
*
L
H
*…*
*…*
*…*
*…*
H or L
H or L
↓
↓
H
H
Notes:
H = high level = -12V, L = low level = 0V, X = irrelevant,
↓
= high-to-low transition,
↑
= low-to-high transition.
* = dependent on previous stage’s state before the last CLK high-to-low transition or last LE high.
4
SUPERTEX [ Supertex, Inc ]
