HV3418
Functional Block Diagram
POL
BL
Latch Enable
V
PP
D
IOA
HV
OUT
1
Clock
HV
OUT
2
•
•
•
60 Additional
Outputs
•
•
•
HV
OUT
63
DIR
64 bit
Static Shift
Register
64 Latches
HV
OUT
64
D
IOB
Function Table
Inputs
Function
Data
X
X
X
H or L
X
X
L
H
D
IOA
D
IOB
CLK
X
X
X
↑
X
X
↑
↑
↑
↑
LE
X
X
L
L
↓
↓
H
H
X
X
BL
L
L
H
H
H
H
H
H
X
X
POL
L
H
L
H
H
L
H
H
X
X
DIR
X
X
X
X
X
X
X
X
L
H
Shift Reg
1
All on
All off
Invert mode
Load S/R
Load/Store Data
in Latches
Transparent
Latch mode
I/O Relation
*
*
*
2…64
*…*
*…*
*…*
1
H
L
*
*
*
*
L
H
—
—
Outputs
HV Outputs
2…64
H…H
L…L
*…*
*…*
*…*
*…*
*…*
*…*
Data Out
*
*
*
*
*
*
*
*
*
D
IOB
D
IOA
H or L *…*
*
*
L
H
Q
n
→
Q
n
→
*…*
*…*
*…*
*…*
Q
n-1
Q
n+1
Notes:
H = high level, L = low level, X = irrelevant,
↑
= low-to-high transition,
↓
= high-to-low transition.
* = dependent on previous stage’s state before the last CLK or last LE high.
4
SUPERTEX [ Supertex, Inc ]
