HV300DB1
HV300DB1 Schematic
+
48V
Input
VEE
R1
487KΩ
UV
R2
9.09KΩ
OV
R3
9.09KΩ
VEE Ramp
Cramp
10nF
Rsense
0.05Ω
Sense Gate
J1
M1
IRFR120N
VDD
+
48V
Output
VDD
PWRGD
PG
Cload
100µF
HV300LG
-
VEE
Drain
-
Bill of Materials for HV300DB1 Demo Board
Designator
J1
R1
R2
R3
R
SENSE
C
RAMP
C
LOAD
M1
HV300
Description
Wire Jumper
Thick film chip resistor
Thick film chip resistor
Thick film chip resistor
Thick film chip resistor
Ceramic chip capacitor, X7R
Electrolytic capacitor
N-Channel MOSFET
Hot Swap IC
487K
9.09K
9.09K
0.05
Value/Rating
--
± 1%
± 1%
± 1%
± 1%
Package
--
0805
0805
0805
1206
0805
--
Dpak
SO-8
Part Number
--
ERJ6ENF487K
ERJ6ENF9.09K
ERJ6ENF9.09K
WSL1206-.05
ECJ-2VB1H103K
ECA-2CHG101
IRFR120N
HV300LG
Panasonic
Panasonic
Panasonic
Dale
Panasonic
Panasonic
International Rectifier
Supertex Inc.
Manufacturer
--
10nF, 50V
100µF, 160V
100V, 0.21
90V
HV300 Typical Waveforms
Notes:
1) Some versions of the HV300DB1 may include a 10nF
capacitor from IC pins 5 to 6 (the MOSFET gate to source).
This capacitor is used to eliminate ringing at the end of the
inrush period.
2) Current can be measured with a current probe on the Vdd
line. The current drawn by the load can be measured by
replacing J1 with a small resistor and measuring the voltage
drop. Alternatively, a current probe can be used by replacing
J1 with a wire loop.
3) PG is an open drain output and will have no effect if probed
without a pullup.
4. The dual plateau characteristic of the gate response is an
intended result of Supertex’s closed loop hot swap solution.
The steep voltage jump of the gate occurs after the MOSFET
is fully on and indicates the point at which the IC goes into
sleep mode (PG high).
Drain
50V/div
V
IN
50V/div
Gate
5.00V/div
I
inrush
500mA/div
5.00ms/div
05/16/01
©2001 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
PB
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
SUPERTEX [ Supertex, Inc ]
