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HV2701_07 参数 Datasheet PDF下载

HV2701_07图片预览
型号: HV2701_07
PDF下载: 下载PDF文件 查看货源
内容描述: 低电荷注入16通道高压模拟开关与泄漏电阻 [Low Charge Injection 16-Channel High Voltage Analog Switch with Bleed Resistors]
分类和应用: 开关高压
文件页数/大小: 8 页 / 710 K
品牌: SUPERTEX [ Supertex, Inc ]
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HV2701  
Pin Configuration  
Ordering Information  
48  
Package Options  
1
DEVICE  
48-Lead LQFP (FG)  
(7x7x1.4mm body, 0.50mm pitch)  
HV2701  
HV2701FG-G  
-G indicates package is RoHS compliant (‘Green’)  
Absolute Maximum Ratings  
48-Lead LQFP Package (FG)  
(top view)  
Parameter  
Value  
-0.5V to +7V  
220V  
VDD Logic supply  
Product Marking  
VPP-VNN differential supply  
VPP Positive supply  
VNN Negative supply  
Logic input voltage  
Analog signal range  
Peak analog signal current/channel  
Storage temperature  
Power dissipation  
Top Marking  
-0.5V to VNN+200V  
+0.5V to -200V  
-0.5V to VDD +0.3V  
VNN to VPP  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
L = Lot Number  
HV2701FG  
LLLLLLLLL  
C = Country of Origin*  
A = Assembler ID*  
Bottom Marking  
3.0A  
-65°C to 150°C  
1.0W  
CCCCCCCC  
AAA  
= “Green” Packaging  
*May be part of top marking  
Absolute Maximum Ratings are those values beyond which damage to the device may occur.  
Functional operation under these conditions is not implied. Continuous operation of the device at  
the absolute rating level may affect device reliability. All voltages are referenced to device ground.  
48-Lead LQFP Package (FG)  
Recommended Operation Conditions  
Symbol  
Parameter  
Value  
VDD  
Logic power supply voltage  
Positive high voltage supply  
Negative high voltage supply  
High level input voltage  
Low level input voltage  
3.0V to 5.5V  
VPP  
+40V to VNN +200V  
-40V to –160V  
0.9VDD to VDD  
VNN  
VIH  
VIL  
0V to 0.1VDD  
Analog signal voltage peak-to-  
peak  
VSIG  
VNN+10V to VPP- 0V  
0°C to 70°C  
TA  
Operating free air temperature  
Notes:  
1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-  
down last.  
2. V must be within V and V or floating during power up/down transition.  
3. RSisIGe and fall times ofNpNower sPuPpplies VDD, VPP, and VNN should not be less than 1.0msec.  
2