HV22716/HV22816
Logic Diagram
LATCHES
D
IN
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
D
LE
CL
LEVEL
SHIFTERS
OUTPUT
SWITCHES
SW0
CLK
SW1
SW2
SW3
8 BIT
SHIFT
REGISTER
SW4
SW5
D
OUT
SW6
SW7
V
NN
V
PP
V
DD
LE
CL
Truth Table
D0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
D1
D2
D3
D4
D5
D6
D7
LE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
CL
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
HOLD PREVIOUS STATE
OFF OFF OFF OFF OFF OFF OFF OFF
Notes:
1. The eight switches operate
independently.
2. Serial data is clocked in on
the L→ H transition CLK.
3. The switches go to a state
retaining their present
condition at the rising edge of
LE. When LE is low the shift
register data flows through
the latch.
4. D
OUT
is high when switch 7 is
on.
5. Shift register clocking has no
effect on the switch states if
LE is H.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
13-88
SUPERTEX [ Supertex, Inc ]
