HV214
Truth Table
Data in 8-Bit Shift Register
D0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D1
D2
D3
D4
D5
D6
D7
LE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
CL
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
OFF
OFF
Hold Previous State
OFF
OFF
OFF
OFF
OFF
OFF
Output Switch State
SW0
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
SW1
SW2
SW3
SW4
SW5
SW6
SW7
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L→H transition CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flows through the latch.
4. D
OUT
is high when switch 7 is on.
5. Shift register clocking has no effect on the switch states if LE is H.
6. The clear input overrides all other inputs.
Logic Timing Waveforms
D
N+1
DATA
IN
50%
D
N
50%
D
N-1
LE
50%
50%
t
WLE
t
SD
50%
50%
t
h
t
DO
CLOCK
t
SU
DATA
OUT
50%
t
OFF
t
ON
OFF
V
OUT
(TYP)
ON
90%
10%
CLR
50%
t
WCL
50%
5
SUPERTEX [ Supertex, Inc ]
