SMT4504
Preliminary Information
PIN DESCRIPTIONS
Pin Name
VCTRL
C
VM
C
VCTRL
D
VM
D
IRQ
HEALTHY
RST
Type
OUT
IN
OUT
IN
OUT
OUT
OUT
Number
1
2
3
4
5
6
7
Function
Control voltage used to track/sequence the converters
Channel C converter output or sense+ line
Control voltage used to track/sequence the converters
Channel D converter output or sense+ line
Programmable active high/low open drain latched output. Asserted when
programmed power supply is in a fault condition.
Programmable active high/low output asserted when all Fault conditions are
clear
Programmable active high/low open drain output signals when all
programmed power supplies are within the monitored limits and the MR signal
is inactive. RST has a programmable timeout period with options for
0.64/50/100/200ms.
Active low open drain I/O connected to LINK_B pin other SMT4504’s for
linked operation
Active low open drain I/O connected to LINK_A pin other SMT4504’s for
linked operation
Ground of the part
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low open drain output. Asserted when the channel is tracking and
between track off and track on.
Active low input internally pulled up to VDD_CAP with 75k ohm resistor
Force shutdown active low I/O used to turn off all converter enable signals.
Do not drive FS# high.
Active high I/O signals the start of the power sequencing. When asserted the
part will sequence the supplies on and when de-asserted the part will
sequence the supplies off. Do not drive PWR_ON high.
External tracking ramp reference
Bi-directional I
2
C Data line
I
2
C Clock line
I
2
C device bus address assignment pin.
I
2
C device bus address assignment pin.
I
2
C device bus address assignment pin.
Programmable active high/low write protect input. When asserted the
configuration registers are write protected and the write protect volatile
register is set.
Active low input. When asserted the RST output will be allowed to de-assert
after a reset timeout if there are no reset sources still active.
Ground of the part
Power supply of the part
LINK_B
LINK_A
GND
STATUS
A
STATUS
B
STATUS
C
STATUS
D
SEATED#
FS#
PWR_ON
VRLINK
SDA
SCL
A0
A1
A2
WP
MR#
GND
VDD
I/O
I/O
PWR
OUT
OUT
OUT
OUT
IN
I/O
I/O
I/O
DATA
CLK
IN
IN
IN
IN
IN
PWR
PWR
8
9
10
11
12
13
14
15
16
17
18
25
26
27
28
29
30
31
34
35
Summit Microelectronics, Inc
2071 1.1 01/07/05
5
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
