SMS48
PreliminaryInformation
2
I C INTERFACE (CONTINUED)
START and STOP Conditions
Whenboththedataandclocklinesarehighthebusissaid
to be not busy. A high-to-low transition on the data line,
while the clock is high, is defined as the Start condition.
A low-to-high transition on the data line, while the clock
is high, is defined as the Stop condition. See Figure 8.
D7
D0
D6
D5
D4
D3
D2
D1
MSB
LSB
Address Bits
Device Type
SMS48
Bus
MSB R/W
x
x
x
x
START
STOP
1
0
0
1
Õ Configuration Register
Table 9. Slave Addresses
Read/WriteBit
Condition
Condition
SCL
SDA In
The last bit of the data stream defines the operation to be
performed. When set to 1 a Read operation is selected;
when set to 0 a Write operation is selected.
Figure 8 - START and STOP Conditions
WRITE OPERATIONS
The SMS48 uses byte Write operations. A byte Write
operation writes a single byte during the nonvolatile write
period(tWR).
Acknowledge (ACK)
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device,
either the Master or the Slave, will release the bus after
transmitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line low to Acknowledge that it
received the eight bits of data. The Master will leave the
SDA line high (NACK) when it terminates a read function.
ByteWrite
AftertheSlaveaddressissent(toidentifytheSlavedevice
andselecteitheraReadorWriteoperation),asecondbyte
is transmitted which contains the low order 8 bit address
of any one of the 256 words in the array. Upon receipt of
the word address the SMS48 responds with an Acknowl-
edge. After receiving the next byte of data it again
responds with an Acknowledge. The Master then termi-
natesthetransferbygeneratingaStopcondition,atwhich
timetheSMS48beginstheinternalWritecycle. Whilethe
internal Write cycle is in progress the SMS48 inputs are
disabled and the device will not respond to any requests
from the Master.
TheSMS48willrespondwithanAcknowledgeafterrecog-
nitionofaStartconditionanditsslaveaddressbyte. Ifboth
the device and a write operation are selected the SMS48
willrespondwithanAcknowledgeafterthereceiptofeach
subsequent 8-Bit word. In the READ mode the SMS48
transmitseightbitsofdata,thenreleasestheSDAline,and
monitorsthelineforanAcknowledgesignal. IfanAcknowl-
edgeisdetectedandnoStopconditionisgeneratedbythe
Master, the SMS48 will continue to transmit data. If a
NACK is detected the SMS48 will terminate further data
transmissionsandawaitaStopconditionbeforereturning
to the standby power mode.
AcknowledgePolling
WhentheSMS48isperforminganinternalWriteoperation
itwillignoreanynewStartconditions. Sincethedevicewill
only return an acknowledge after it accepts the Start the
part can be continuously queried until an acknowledge is
issued,indicatingthattheinternalWritecycleiscomplete.
Seetheflowchartforthepropersequenceofoperationsfor
polling.
Device Addressing
Following a Start condition the Master must output the
address of the Slave it is accessing. The most significant
four bits of the Slave address are the device type
identifier/address. For the SMS48 the default is 1001BIN
.
The next two bits are the Bus Address. The next bit (the
7th) is the MSB of the configuration address.
SUMMIT MICROELECTRONICS, Inc.
2088 1.1 04/10/05
12
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
