SMS48
PreliminaryInformation
PIN DESCRIPTIONS
V0, V1, V2, V3 (16, 2, 3, 14)
These inputs are used as the voltage monitor inputs and
as the voltage supply for the SMS48. Internally they are
activelydiodeORedandtheinputwiththehighestvoltage
potential will be the default supply voltage (VDD_CAP).
V
PTH-UV
V
— V
3
0
t
t
DRST
The RESET# outputs will be valid if any one of the four
inputs is above 1V. However, for full device operation at
least one of the inputs must be at 2.7V or higher.
PRTO
RESET#
The sensing threshold for each input is independently
programmable in 5mV increments from 0.6V to 1.875V or
15mV increments from 1.8V to 5.625V. Also, the occur-
renceofanunder-orover-voltageconditionthatisdetected
asaresultofthethresholdsettingcanbeusedtogenerate
aRESET#0-3. Theprogrammablenatureofthethreshold
voltage eliminates the need for external voltage divider
networks.
Figure 3 - RESET# Timing
VDD_CAP(12)
TheVDD_CAPpinconnectstotheinternalsupplyvoltage
for the SMS48. A capacitor is placed on this pin to filter
supply noise as well as hold up the device in the event of
powerfailure. Thevoltageonthisnodeisdeterminedbythe
highest input voltage. Loading of this pin should be
minimized to prevent excessive power dissipation in the
part.
GND
Power supply return.
MR# (1)
The manual reset input always generates a RESET#0-3
output whenever it is driven low. The duration of the
RESET#outputpulsewillbeinitiatedwhenMR#goeslow
and it will stay low for the duration of MR# low pulse plus
theprogrammedresettime-outperiod(tPRTO). MR#must
be held low during a configuration register write or read.
This signal is pulled up internally through a 50kΩ resistor.
WLDI(15)
Watchdoginput. AlowtohightransitionontheWLDIinput
will clear the watchdog timer, effectively starting a new
time-out period. This signal is pulled up internally through
a 50kΩ resistor.
IfWLDIisstucklowandnolow-to-hightransitionisreceived
withintheprogrammedtPWDTO period(programmedwatch
dog time-out) the RESET#0-3 outputs will be driven low.
RESET#0-3 (11, 4, 5, 13)
Theresetoutputsareactivelowopendrainoutputs. They
aredrivenlowwhenevertheMR#inputisloworwhenever
atriggeringunder-voltageorover-voltageconditionexists
onthecorrespondinginputchannelorwhentheWatchdog
timer expires. The four voltage monitor inputs are always
functioning,buttheirabilitytogeneratearesetisprogram-
mable(configurationregister4).RefertoFigures2,3and
5foradetailedillustrationoftherelationshipbetweenMR#,
RESET#0-3 and the VIN levels.
HoldingWLDIhighwillnotblocktheWatchdogfromtiming
outandgeneratingareset. RefertoFigure4foradetailed
illustration of the relationship between RESET#0-3 and
WLDI.
A1, A2 (6, 7)
A1 and A2 are the address inputs. When addressing the
SMS48 configuration registers, the address inputs distin-
guish which one of four possible devices sharing the
common bus is being addressed.
MR#
SDA(9)
SDA is the serial data input/output pin. It should be tied to
t
DMRRST
VDD_CAP through a pull-up resistor.
t
RESET#
PRTO
Figure 2 - RESET# Timing with MR#
SUMMIT MICROELECTRONICS, Inc.
2088 1.1 04/10/05
6
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
