欢迎访问ic37.com |
会员登录 免费注册
发布采购

SMS48GR05 参数 Datasheet PDF下载

SMS48GR05图片预览
型号: SMS48GR05
PDF下载: 下载PDF文件 查看货源
内容描述: 四可编程精密监控器具有独立的复位 [Quad Programmable Precision Supervisory Controller With Independent Resets]
分类和应用: 监控
文件页数/大小: 16 页 / 841 K
品牌: SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
 浏览型号SMS48GR05的Datasheet PDF文件第7页浏览型号SMS48GR05的Datasheet PDF文件第8页浏览型号SMS48GR05的Datasheet PDF文件第9页浏览型号SMS48GR05的Datasheet PDF文件第10页浏览型号SMS48GR05的Datasheet PDF文件第12页浏览型号SMS48GR05的Datasheet PDF文件第13页浏览型号SMS48GR05的Datasheet PDF文件第14页浏览型号SMS48GR05的Datasheet PDF文件第15页  
SMS48  
PreliminaryInformation  
2
I C INTERFACE  
InputDataProtocol  
CONFIGURATION REGISTER OPERATION  
The protocol defines any device that sends data onto the  
bus as a transmitter and any device that receives data as  
a receiver. The device controlling data transmission is  
called the Master and the controlled device is called the  
Slave. InallcasestheSMS48willbeaSlavedevice,since  
it never initiates any data transfers.  
Datafortheconfigurationregistersarereadandwrittenvia  
an industry standard two-wire interface. The bus was  
designed for two-way, two-line serial communication be-  
tween different integrated circuits. The two lines are a  
serial data line (SDA) and a serial clock line (SCL). The  
SDA line must be connected to a positive supply by a pull-  
upresistor,locatedsomewhereonthebus. SeeOperating  
Characteristics: Table 8 and Figure 7.  
One data bit is transferred during each clock pulse. The  
data on the SDA line must remain stable during clock high  
time because changes on the data line while SCL is high  
will be interpreted as start or stop condition.  
Symbol  
fSCL  
Parameter  
SCL clock frequency  
Clock low period  
Conditions  
MIN  
0
TYP  
MAX  
Units  
kHz  
µs  
100  
tLOW  
tHIGH  
tBUF  
4.7  
4.0  
4.7  
4.7  
4.0  
4.7  
0.2  
0.2  
Clock high period  
µs  
Bus free time (1)  
Before new transmission  
µs  
tSU:STA  
tHD:STA  
tSU:STO  
tAA  
Start condition setup time  
Start condition hold time  
Stop condition setup time  
Clock edge to valid output  
Data Out hold time  
µs  
µs  
µs  
SCL low to valid SDA (cycle n)  
3.5  
µs  
tDH  
SCL low (cycle n+1) to SDA change  
µs  
tR  
SCL and SDA rise time (1)  
SCL and SDA fall time (1)  
Data In setup time  
1000  
300  
ns  
tF  
ns  
tSU:DAT  
tHD:DAT  
TI  
250  
0
ns  
Data In hold time  
ns  
Noise filter SCL and SDA  
Write cycle time  
Noise suppression  
100  
ns  
tWR  
5
ms  
Note (1): These values are guaranteed by design.  
Table 8. I2C Operating Characteristics  
t
t
LOW  
HIGH  
t
t
R
F
SCL  
t
t
t
t
SU:STO  
t
HD:DAT  
SU:STA  
SU:DAT  
HD:STA  
t
BUF  
SDA In  
t
t
AA  
DH  
SDA Out  
Figure 7 - I2C Operating Characteristics  
SUMMIT MICROELECTRONICS, Inc.  
2088 1.1 04/11/05  
11