SMS46
PreliminaryInformation
2
I C INTERFACE (CONTINUED)
The high order bits of the address byte remain constant. ten. AswiththebyteWriteoperation,allinputsaredisabled
during the internal Write cycle. Refer to Figure 11 for the
address, Acknowledge, and data transfer sequence.
Should the Master transmit more than 16 bytes, prior to
generating the Stop condition, the address counter will
rollover and the previously written data will be overwrit-
S
Typical Write Operation
(Standard memory device type)
T
A
R
T
S
T
O
P
Device Type Bus
Address Address
Master
SDA
R
/
W
B B
A
D D D D D D D D
A
7
A A A A A A A
6 5 3 2 1 0
A A
1 0 1 0
7
6
5
4
3
2
1
0
4
8
2
1
A
C
K
A
C
K
A
C
K
Slave
Up to 15
additional bytes
can be written
before issuing
the stop.
S
T
A
R
T
S
N
S
A
T
T
A
R
T
Typical Reading Operation
(Alternate memory device type)
A
C
K
C
O
K
P
Master
SDA
B B
A A
R
/
W
B B
A A
R
/
W
A
8
D D D D D D D D
A A A A A A A A
A
8
1 1
1 0
1 1
1 0
7
6 5 4 3 2 1 0
7
6 5 4 3 2 1 0
2
1
2
1
A
C
K
A
C
K
Slave
S
T
A
R
T
S
Writing Configuration Registers
T
Master
SDA
O
P
R
/
B B
A A
D D D D D D D D
C C C C C C C C
X
0 1
1 0
7
6 5 4 3 2 1 0
7
6
5
4
3
2
1
0
W
2
1
A
C
K
A
C
K
A
C
K
Slave
S
T
A
R
T
S
T
A
R
T
N
A
C
K
S
T
O
P
A
C
K
Reading the Configuration Register
Master
SDA
B B
A A
R
B B
A A
R
/
W
D D D D D D D D
C C C C C C C C
X
/
X
0 1
1 0
0 1
1 0
7
6 5 4 3 2 1 0
7
6 5 4 3 2 1 0
2
1
W
2
1
A
C
K
A
C
K
Slave
2047 Fig11
Figure 9 - Read and Write Operations
SUMMIT MICROELECTRONICS, Inc.
2083 1.1 06/04/04
13
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
