SMS46
PreliminaryInformation
2
I C INTERFACE (CONTINUED)
START and STOP Conditions
D7
MSB
D0
LSB
D6
D5
D4
D3
D2
D1
Whenboththedataandclocklinesarehighthebusissaid
to be not busy. A high-to-low transition on the data line,
while the clock is high, is defined as the Start condition.
A low-to-high transition on the data line, while the clock
is high, is defined as the Stop condition. See Figure 8.
Address Bits
Device Type
SMS46
Bus
MSB R/W
x
x
x
x
1
1
1
0
0
0
0
1
1
1
0
1
Õ Configuration Register
Õ Memory (default)
START
Condition
STOP
Condition
Õ Alternate Memory
SCL
Table 9. Slave Addresses
SDA In
Read/WriteBit
The last bit of the data stream defines the operation to be
performed. When set to 1 a Read operation is selected;
when set to 0 a Write operation is selected.
2047 Fig10
Figure 8 - START and STOP Conditions
WRITEOPERATIONS
Acknowledge (ACK)
The SMS46 allows two types of Write operations: byte
Write and page Write. A byte Write operation writes a
single byte during the nonvolatile write period (tWR). The
page Write operation, limited to the memory array, allows
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device,
either the Master or the Slave, will release the bus after
transmitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line low to Acknowledge that it
received the eight bits of data. The Master will leave the
SDA line high (NACK) when it terminates a read function.
up to 16 bytes in the same page to be written during tWR
.
Byte Write
After the Slave address is sent (to identify the Slave
device and select either a Read or Write operation), a
second byte is transmitted which contains the low order
8 bit address of any one of the 512 words in the array.
UponreceiptofthewordaddresstheSMS46respondswith
an Acknowledge. After receiving the next byte of data it
again responds with an Acknowledge. The Master then
terminates the transfer by generating a Stop condition, at
which time the SMS46 begins the internal Write cycle.
While the internal Write cycle is in progress the SMS46
inputs are disabled and the device will not respond to any
requests from the Master.
TheSMS46willrespondwithanAcknowledgeafterrecog-
nitionofaStartconditionanditsslaveaddressbyte. Ifboth
the device and a write operation are selected the SMS46
willrespondwithanAcknowledgeafterthereceiptofeach
subsequent 8-Bit word. In the READ mode the SMS46
transmitseightbitsofdata,thenreleasestheSDAline,and
monitorsthelineforanAcknowledgesignal. IfanAcknowl-
edgeisdetectedandnoStopconditionisgeneratedbythe
Master, the SMS46 will continue to transmit data. If a
NACK is detected the SMS46 will terminate further data
transmissionsandawaitaStopconditionbeforereturning
to the standby power mode.
Page Write (memory only)
Device Addressing
The SMS46 is capable of a 16-byte page Write operation.
It is initiated in the same manner as the byte Write
operation, but instead of terminating the Write cycle after
the first data word the Master can transmit up to 15 more
bytesofdata. AfterthereceiptofeachbytetheSMS46will
respondwithanAcknowledge.
Following a Start condition the Master must output the
address of the Slave it is accessing. The most significant
four bits of the Slave address are the device type
identifier/address. For the SMS46 the default is 1010BIN
.
The next two bits are the Bus Address. The next bit (the
7th) is the MSB of the memory address.
The SMS46 automatically increments the address for
subsequentdatawords. Afterthereceiptofeachwordthe
low order address bits are internally incremented by one.
SUMMIT MICROELECTRONICS, Inc.
2083 1.1 06/04/04
12
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
