SMS45
PreliminaryInformation
CONFIGURATION REGISTERS (CONTINUED)
D3
MSB
D0
LSB
D2
D1
D7
MSB
Read1
Only
D6
D5
D4
D3
Action
V3
0
V2
V1
V0
0
Read Read
Only Only
Writing a 0 enables
undervoltage detection for
the selected V input
RTO1 RTO0
Action
0
1
0
1
0
0
0
0
0
0
1
1
0
1
0
1
x
x
x
x
x
x
x
x
tPRTO = 25ms
tPRTO = 50ms
PRTO = 100ms
PRTO = 200ms
Writing a 1 enables
overvoltage detection for
the selected V input
1
1
t
t
Table 3. Configuration Register 5 (D0 through D3)
WATCHDOG TIMER
Table 5. Configuration Register 6 (D3 through D7)
Note 1 - Read Only bit D7 is set to a 0. Read only bits
D4 and D3 are revision control and the value indi-
cates the status code of the device (ie. 01 is status
code 1).
The Watchdog Timer will generate a reset if it times out. It
can be cleared by a high-to-low transition on WLDI and
restarted.
If the Watchdog times out RESET# will be driven low until
tPRTO at which time it will return high. Refer to Figure 4
which illustrates the action of RESET# with respect to the
Watchdog timer and the WLDI input.
D0
D2
D1
LSB
Action
OFF
WD2
WD1 WD0
IfWLDIisheldlowthetimerwillfree-rungeneratingaseries
of resets.
0
0
1
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
D7
MSB
D4
LSB
400ms
800ms
1600ms
3200ms
6400ms
D6
D5
Action
V3
0
V2
0
V1
0
V0
0
Reading a 1 indicates a
supply fault
1
1
1
1
Table 6. Configuration Register 6 (D0, D1, D2)
Table 4. Configuration Register 5 (D4 through D7)
The delay from VPTH0 until PUP#1 low is tPDLY1. There is
a similar tPDLYX delay for V1 to PUP#2 and for V2 to
PUP#3. Theyareprogrammedinregister7. Cascadingwill
always occur as indicated in the flow chart (Figure 7).
WhentheWatchdogtimesoutRESET#willbegenerated.
WhenRESET#returnshigh(aftertPRTO)thetimerisreset
to time zero.
Register6isalsousedtosettheprogrammableresettime-
out period (tPRTO) and to select the cascade option.
CascadeDelayProgramming
Thecascadedelaysareprogrammedinregister7. Bit7of
register6mustbesettoa0inordertoenablethecascading
of the PUP# outputs. Cascading will not commence until
V0 is above its programmed threshold.
EachPUP#(-3,-2and-1)isdelayedaccordingtothestates
ofitsBit1andBit0asindicatedinTable9. RefertoFigures
1 and 5 for the detailed timing relationship of the program-
mablepower-oncascading.
SUMMIT MICROELECTRONICS, Inc.
2079 1.2 05/24/04
11
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
