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SMS2902SA 参数 Datasheet PDF下载

SMS2902SA图片预览
型号: SMS2902SA
PDF下载: 下载PDF文件 查看货源
内容描述: 电压监控电路,看门狗定时器 [Voltage Supervisory Circuit With Watchdog Timer]
分类和应用: 监控
文件页数/大小: 14 页 / 157 K
品牌: SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
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SMS2902/SMS2904/SMS2916
The next three bits are the high order address bits on the
2904 and 2916 and are “Don’t Care” on the 2902.
Read/Write Bit
The last bit of the data stream defines the operation to be
performed. When set to “1,” a read operation is selected;
when set to “0,” a write operation is selected.
WRITE OPERATIONS
The SMS29xx allows two types of write operations: byte
write and page write. The byte write operation writes a
single byte during the nonvolatile write period (t
WR
). The
page write operation allows up to 16 bytes in the same
page to be written during t
WR
.
Byte WRITE
Upon receipt of both the slave address and word address,
the SMS29xx responds with an ACKnowledge for each.
After receiving the next byte of data, it again responds with
an ACKnowledge. The master then terminates the trans-
fer by generating a STOP condition, at which time the
SMS29xx begins the internal write cycle.
While the internal write cycle is in progress, the SMS29xx
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 7 for the
address, ACKnowledge and data transfer sequence.
Page WRITE
The SMS29xx is capable of a 16-byte page write opera-
tion. It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word, the master can transmit up to 15 more
bytes of data. After the receipt of each byte, the SMS29xx
will respond with an ACKnowledge.
The SMS29xx automatically increments the address for
subsequent data words. After the receipt of each word,
the low order address bits are internally incremented by
one. The high order five bits of the address byte remain
constant. Should the master transmit more than 16 bytes,
prior to generating the STOP condition, the address
counter will “roll over,” and the previously written data will
be overwritten. As with the byte-write operation, all inputs
are disabled during the internal write cycle. Refer to
Figure 7 for the address, ACKnowledge and data transfer
sequence.
Acknowledges Transmitted from
SMS29xx to Master Receiver
If single byte-write only,
Stop bit issued here.
Acknowledges Transmitted from
SMS29xx to Master Receiver
SDA
Bus
Activity
1010
A A X R
10 9
W
A
C
Word Address
K
A A A A A A A A
7 6 5 4 3 2 1 0
A
C
K
Data Byte n
A
C
K
A
Data Byte n+1
C
K
D D D D D D D D
7 6 5 4 3 2 1 0
Data Byte n+15
C
K
D D D D D D D D
7 6 5 4 3 2 1 0
A
A A
X
10 9
0
D D D D D D D D
7 6 5 4 3 2 1 0
S
T Device
Type
A
R Address
Read/Write
T
0= Write
S
T
O
P
Slave Address
Master Sends Read
Request to Slave
Master Writes Word
Address to Slave
Master Writes
Data to Slave
Master Writes
Data to Slave
Master Writes
Data to Slave
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
2028 ILL9.1
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Shading Denotes
SMS29xx
SDA Output Active
FIGURE 7. PAGE/BYTE WRITE MODE
2028 5.1 8/2/00
8