SMS1242
DEVICE OPERATION
The SMS1242 provides a precision reset function for a
microcontroller or microprocessor during power-up,
power-down and brown-out conditions. The device will
monitor two independent voltage supplies and will gener-
ate a reset condition when either supply is invalid. It is
configured with two outputs, both driven by the same
conditions. They are open drain and will track each other
but the outputs are not internally tied together.
Because RESET1# and RESET2# are essentially open
drain outputs (RESET1# has a weak internal pullup,
RESET2# does not) they can be independently driven low
by external signals. This can be very useful in a dual
processor system or in a combined processor/ASIC sys-
tem where, either for system operation or system test, the
processors or ASICs must be independently held in reset
without resetting the other portion of the system.
SUPPLY MONITOR
(Assume V
SENSE
> V
SNS
) During power-up the SMS1242
monitors the supply voltage. The RESET1# and RE-
SET2# outputs are guaranteed to be driven low once V
CC
reaches 1V. As V
CC
rises RESET1# and RESET2#
remain asserted until V
CC
reaches the V
RST
threshold. As
V
CC
passes through V
RST
an internal timer is started to
continue driving the outputs for an additional 150ms
(nominal).
If a power-fail or brown-out condition occurs (V
CC
< V
RST
)
RESET1# and RESET2# will be asserted. They will
remain active so long as V
CC
is below V
RST
. Because the
internal timer will be continuously reset so long as V
CC
is
below V
RST
, a brownout condition that interrupts a previ-
ously initiated reset pulse causes an additional reset delay
from the time the V
CC
passes back through V
RST
.
During power down conditions, once V
CC
drops below
V
RST
, RESET1# and RESET2# are guaranteed to be
asserted for V
CC
≥
1V.
V
SENSE
MONITOR
(Assume V
CC
is >V
RST
) The SMS1242 continuously
monitors the VSENSE input. The RESET1# and RE-
SET2# outputs will be driven low so long as V
SENSE
is <
VSNS. As V
SENSE
passes through V
SNS
an internal timer
is started to continue driving the outputs for an additional
150ms (nom.).
If a power-fail condition occurs (V
SENSE
falls below V
SNS
)
RESET1# and RESET2# will be asserted. They will re-
main active so long as V
SENSE
is below V
SNS
. Because
the internal timer will be continuously reset so long as
V
SENSE
is below V
SNS
, a brownout condition that inter-
rupts a previously initiated reset pulse causes an addi-
tional reset delay from the time V
SENSE
becomes greater
than V
SNS
.
MANUAL RESET
The manual reset input allows RESET1# and RESET2# to
be activated by a pushbutton switch. The switch is
effectively debounced by the 100ms minimum t
RST
(RE-
SET pulse width). MR# can also be driven by an external
logic input that meets the 50ns minimum pulse width
required.
Unregulated
+12V DC
DC to DC
Converter
3.3V Out
3.3V
MCU
VCC
VSENSE
MCU #1
RESET1#
MR#
VCC
RESET1#
SMS1242
SMS1242
Test Point #1
MR#
RESET2#
ASIC or MCU #2
1.8V
RESET2#
VSENSE
Low Voltage
High Speed
ASIC
Test Point #2
2038 ILL7.0
2038 ILL8.0
Figure 5. Typical Multi-MCU Implementation
2038 2.0 6/8/00
Figure 6. Typical Dual Voltage Implementation
5
SUMMIT MICROELECTRONICS, Inc.
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
