SMS1242
Symbol
f
SCL
t
LOW
t
HIGH
t
BUF
t
SU:STA
t
HD:STA
t
SU:STO
t
AA
t
DH
t
R
t
F
t
SU:DAT
t
HD:DAT
TI
t
WR
Parameter
SCL clock frequency
Clock low period
Clock high period
Bus free time
Start condition setup time
Start condition hold time
Stop condition setup time
Clock edge to valid output
Data Out hold time
SCL and SDA rise time
SCL and SDA fall time
Data In setup time
Data In hold time
Noise filter SCL and SDA
Write cycle time
Conditions
Min.
0
4.7
4.0
Max.
100
Units
kHz
µs
µs
µs
µs
µs
µs
Before new transmission
4.7
4.7
4.0
4.7
SCL low to valid SDA (cycle n)
SCL low (cycle n+1) to SDA change
0.3
0.3
3.5
µs
µs
1000
300
250
0
Noise suppresion
100
5
ns
ns
ns
ns
ns
ms
2038 Table01 2.0
tR
tF
tHIGH
tLOW
SCL
tSU:SDA
tHD:DAT
tSU:DAT
tSU:STO
tHD:SDA
tBUF
SDA In
tAA
tDH
SDA Out
2038 Fig07 2.0
Figure 7. Memory Timing
SUMMIT MICROELECTRONICS, Inc.
2038 2.0 6/8/00
6
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
