SMM764
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Notes
Min
Typ
Max
Unit
V
0.8 x
Input high voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#)3
Internally regulated to 3.6V
VDD_CAP
VIH
0.7 x
Internally regulated to 5.5V
Internally regulated to 3.6V
Internally regulated to 5.5V
V
V
V
VDD_CAP
0.2 x
Input low voltage (MR#, SDA,
SCL, PWR_ON, SEQ_LINK,
FS#)3
VDD_CAP
VIL
0.3 x
VDD_CAP
Open drain outputs (RST#,
FS#, PWR_ON, HEALTHY,
FAULT#, PUPx, SEQ_LINK)
VOL
IOL
ISINK = 1mA
0
0.4
V
Note – Total ISINK from all PUPx pins
should not exceed 3mA or ADOCACC
specification will be affected
Output low current
0
1.0
mA
VSENSE
VMONITOR
Positive sense voltage
Monitor threshold step size
VM pin
+0.3
VDD_CAP
V
mV
oC
oC
VM, AIN1/AIN2 pins
Commercial temp range
Industrial temp range
5
-3
-5
+3
+5
Internal temperature sensor
accuracy
tSA
Temperature threshold step
tMONITOR
VREF
Internal temp sensor
0.25
1.25
oC
size
Internal 1.25 VREF output
1.24
1.26
V
voltage
-0.25
-0.15
+0.25
+0.15
%
%
–40°C to +85°C
0°C to +70°C
Internal VREF temperature
coefficient
TC
VREF ACC Internal VREF accuracy
-0.4
0.5
+0.4
%
V
Ext VREF
External VREF voltage range
VDD_CAP
External VREF=1.25V,
±0.1%, total PUPx ISINK
<
<
-0.2
0.1
+0.2
%
3ma, VSENSE < 3.5V
ADOC (Active DC Output
Control)/margin accuracy
External VREF=1.25V,
±0.1%, total PUPx ISINK
ADOCACC
-0.5
-0.5
0.3
0.3
+0.5
+0.5
%
%
3ma, VSENSE > 3.5V
Internal VREF=1.25V, total
PUPx ISINK < 3ma
VDD_CAP voltage at which
the PUP, RST#, HEALTHY
and FAULT#, FS#, PWR_ON
SEQ_LINK, outputs are valid
VOUT_VALID
UVLO
Minimum output valid voltage
1
V
VDD_CAP rising
VDD_CAP falling
2.6
2.5
V
V
UVLO (Under Voltage Lockout)
threshold4
Note 1 – Range depends on internal regulator set to 3.6V or 5.5V see 12VIN specification.
Note 2 – See Application Note 37 which describes the type of capacitors to use to obtain minimum leakage.
Note 3 – All logic levels are derived with respect to the voltage present on VDD_CAP, when supplied from the VDD input VDD_CAP is equal to
VDD, under no load.
Note 4 – (100mV typ Hysteresis)
Summit Microelectronics, Inc
2098 1.1 6/29/2005
9
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
