SMM665B
Preliminary Information
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100/400kHz
Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.
See Figure 4 Timing Diagram.
Conditions
100kHz
400kHz
Symbol Description
Min Typ
Max
Min Typ
Max Units
fSCL
SCL Clock Frequency
0
100
0
400
KHz
tLOW
tHIGH
Clock Low Period
Clock High Period
4.7
4.0
1.3
0.6
μs
μs
Before New Transmission
tBUF
Bus Free Time
4.7
4.7
1.3
0.6
μs
μs
- Note 1/
Start Condition Setup
Time
tSU:STA
tHD:STA
tSU:STO
tAA
Start Condition Hold Time
Stop Condition Setup Time
4.0
4.7
0.6
0.6
μs
μs
SCL low to valid
SDA (cycle n)
SCL low (cycle n+1)
to SDA change
Note 1/
Clock Edge to Data Valid
Data Output Hold Time
0.2
0.2
3.5
0.2
0.2
0.9
μs
tDH
μs
tR
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
1000
300
1000
300
ns
ns
ns
ns
ns
Note 1/
tF
tSU:DAT
tHD:DAT
TI
250
0
150
0
Data In Hold Time
Noise Filter SCL and SDA Noise suppression
100
100
Configuration
Registers
tWR_CONFIG Write Cycle Time Config
10
5
10
5
ms
ms
tWR_EE
Write Cycle Time EE
Memory Array
Note: 1/ - Guaranteed by Design.
TIMING DIAGRAMS
tWR (For W rite Operation Only)
tHIGH
tLOW
tR
tF
SCL
tBUF
tHD:DAT
tSU:DAT
tSU:SDA
tSU:STO
tHD:SDA
SDA
(IN)
tAA
tDH
SDA
(OUT)
Figure 4 - Basic I2C Serial Interface Timing
Summit Microelectronics, Inc
2089 2.1 5/25/2011
11