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SMM605 参数 Datasheet PDF下载

SMM605图片预览
型号: SMM605
PDF下载: 下载PDF文件 查看货源
内容描述: 六通道电源电压Marginer和有源直流输出控制器( ADOCTM ) [Six-Channel Supply Voltage Marginer and Active DC Output Controller (ADOCTM)]
分类和应用: 控制器
文件页数/大小: 23 页 / 899 K
品牌: SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
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SMM605  
Preliminary Information  
I2C PROGRAMMING INFORMATION  
SERIAL INTERFACE  
Any access to the SMM605 on the I2C bus will  
temporarily halt the monitoring function. The SMM605  
halts the monitor function from when it acknowledges  
the address byte until a valid stop is received.  
Access to the configuration registers, general-purpose  
memory and command and status registers is carried  
out over an industry standard 2-wire serial interface  
(I2C). SDA is a bi-directional data line and SCL is a  
clock input. Data is clocked in on the rising edge of  
SCL and clocked out on the falling edge of SCL. All  
data transfers begin with the MSB. During data  
transfers SDA must remain stable while SCL is high.  
Data is transferred in 8-bit packets with an intervening  
clock period in which an Acknowledge is provided by  
WRITE  
Writing to the memory or a configuration register is  
illustrated in Figures 11, 12, 13, 17 and 18. A Start  
condition followed by the address byte is provided by  
the host; the SMM605 responds with an Acknowledge;  
the host then responds by sending the memory  
address pointer or configuration register address  
pointer; the SMM605 responds with an acknowledge;  
the host then clocks in on byte of data. For memory  
and configuration register writes, up to 15 additional  
bytes of data can be clocked in by the host to write to  
consecutive addresses within the same page. After  
the last byte is clocked in and the host receives an  
Acknowledge, a Stop condition must be issued to  
initiate the nonvolatile write operation.  
the device receiving data. The SCL high period (tHIGH  
)
is used for generating Start and Stop conditions that  
precede and end most transactions on the serial bus.  
A high-to-low transition of SDA while SCL is high is  
considered a Start condition while a low-to-high  
transition of SDA while SCL is high is considered a  
Stop condition.  
The interface protocol allows operation of multiple  
devices and types of devices on a single bus through  
READ  
unique device addressing.  
The address byte is  
The address pointer for the configuration registers,  
memory, command and status registers must be set  
before data can be read from the SMM605. This is  
accomplished by issuing a dummy write command,  
which is simply a write command that is not followed  
by a Stop condition. The dummy write command sets  
the address from which data is read. After the dummy  
write command is issued, a Start command followed  
by the address byte is sent from the host. The host  
then waits for an Acknowledge and then begins  
clocking data out of the slave device. The first byte  
read is data from the address pointer set during the  
dummy write command. Additional bytes can be  
clocked out of consecutive addresses with the host  
providing an Acknowledge after each byte. After the  
data is read from the desired registers, the read  
operation is terminated by the host holding SDA high  
during the Acknowledge clock cycle and then issuing a  
Stop condition. Refer to Figures 14, 16, 19 and 21 for  
an illustration of the read sequence.  
comprised of a 4-bit device type identifier (slave  
address) and a 3-bit bus address. The remaining bit  
indicates either a read or a write operation. Refer to  
Table 1 for a description of the address bytes used by  
the SMM605.  
The device type identifier for the memory array is  
generally set to 1010BIN following the industry standard  
for a typical nonvolatile memory. There is an option to  
change the identifier to 1011BIN allowing it to be used  
on a bus that may be occupied by other memory  
devices. The configuration registers are grouped with  
the memory array and thus use 1010BIN or 1011BIN as  
the device type identifier. The command and status  
registers are accessible with the separate device type  
identifier of 1001BIN  
.
The bus address bits A[1:0] are programmed into the  
configuration registers. Bus address bit A[2] can be  
programmed as either 0 or biased by the A2 pin. The  
bus address accessed in the address byte of the serial  
data stream must match the setting in the SMM605  
and on the A2 pin.  
Summit Microelectronics, Inc  
2064 1.1 09/16/03  
15