SMM205
Preliminary Information
PIN DESCRIPTIONS
Pin
Number
28
1
2
4
6
8
10
15, 18
16, 20
14, 17
Pin
Type
DATA
CLK
I
I
I
I
CAP
CAP
O
I
Pin Name
SDA
SCL
A2
A1
A0
WP#
FILT_CAP
TRIM_CAPx
TRIMx
VMx
I
2
C Bi-directional data line.
I
2
C clock input.
The address pins are biased either to VDD_CAP or GND. When
communicating with the SMM205 over the 2-wire bus these pins provide a
mechanism for assigning a unique bus address.
Write Protect active low input. When asserted writes to the configuration
registers and general purpose EE are not allowed.
External capacitor input used to filter the VM inputs.
External capacitor input used for Active Control and margining.
Output voltage used to control and/or margin converter voltages. Connect
to the converter trim input.
Voltage monitor input. Connect to the DC/DC converter positive sense line
or its +Vout pin.
Voltage reference input used for DC output control and margining.
VREF_CNTL can be programmed to output the internal 1.25V reference
voltage. Pin should be left open if using VREF internal.
Power supply of the part.
Ground of the part. The SMM205 ground pin should be connected to the
ground of the device under control or to a star point ground. PCB layout
should take into consideration ground drops.
12V power supply input internally regulated to either 3.6V or 5.5V. When
using the 3.6V internal regulator option the voltage input can be as low as
8V. It can be as high as 15V using the 5.5V internal regulator.
Programmable active high/low input. The START input is used solely for
enabling Active Control and/or margining.
Programmable active high/low open drain output indicates that VM is at its
set point. When programmed as an active high output READY can also be
used as an input. When pulled low it will latch the state of the comparator
inputs.
External capacitor input used to filter the internal supply rail.
COMP1 and COMP2 are high impedance inputs, each connected internally
to a comparator and compared against the VREF_CNTL input. Each
comparator can be independently programmed to monitor for UV or OV.
The monitor level is set externally with a resistive voltage divider.
When either of the COMP1 or COMP2 inputs are in fault the open-drain
FAULT# output will be pulled low. A configuration option exists to disable
the FAULT# output while the device is margining.
No Connect. Leave floating; do not connect anything to the NC pins.
2069 1.4 6/23/03
Pin Description
9
21
7
I
PWR
GND
VREF_CNTL
VDD
GND
22
PWR
12VIN
3
I
START
5
I/O
READY
23
19
12
CAP
I
I
VDD_CAP
COMP1
COMP2
11
13, 24-27
O
NC
FAULT#
NC
Summit Microelectronics, Inc
4
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
