SMM205
Preliminary Information
INTERNAL BLOCK DIAGRAM
VREF_CNTL
9
MUX
VREF
CMP
OUTPUT
CONTROL
5
READY
11 FAULT#
TRIM
DRIVE A
20
TRIMA
COMP1 19
COMP2
SDA
SCL
A0
A1
A2
START
WP#
12
28
1
6
4
2
3
8
I
2
C
INTER-
FACE
CMP
CMP
18 TRIM_CAPA
16
TRIM
DRIVE B
INPUT VOLTAGE
SENSING AND
SIGNAL
CONDITIONING
EE
CONFIGURATION
REGISTERS
AND MEMORY
TRIMB
15 TRIM_CAPB
14 VMA
17 VMB
VDD
21
VDD_CAP 23
SUPPLY
ARBITRATION
10 FILT_CAP
12VIN 22
3.6V / 5V
REGULATOR
7
GND
Figure 3 –Block Diagram.
PACKAGE AND PIN CONFIGURATION
28 Pin QFN
Top View
SDA
NC
NC
NC
NC
VDD_CAP
12VIN
28 27 26 25 24 23 22
1
2
3
4
5
6
7
8
9 10 11 12 13 14
21
20
19
18
17
16
15
Pin 1
SCL
A2
START
A1
READY
A0
GND
SMM205
VDD
TRIMA
COMP1
TRIM_CAPA
VMB
TRIMB
TRIM_CAPB
Summit Microelectronics, Inc
WP#
VREF_CNTL
FILT_CAP
FAULT#
COMP2
NC
VMA
2069 1.4 6/23/03
3