SMM205
Preliminary Information
INTERNAL BLOCK DIAGRAM
9
VREF_CNTL
MUX
5
CMP
READY
VREF
11
FAULT#
OUTPUT
CONTROL
19
12
COMP1
COMP2
20
18
CMP
CMP
TRIM
TRIMA
DRIVE A
TRIM_CAPA
16
15
TRIMB
SDA 28
TRIM
DRIVE B
TRIM_CAPB
SCL
A0
1
6
4
2
3
8
INPUT VOLTAGE
SENSING AND
SIGNAL
14
17
VMA
VMB
I2C
INTER-
FACE
A1
A2
CONDITIONING
EE
CONFIGURATION
REGISTERS
START
WP#
AND MEMORY
21
23
VDD
SUPPLY
ARBITRATION
VDD_CAP
10 FILT_CAP
GND
3.6V / 5V
22
12VIN
7
REGULATOR
Figure 3 –Block Diagram.
PACKAGE AND PIN CONFIGURATION
28 Pin QFN
Top View
Pin 1
28
26 25
23 22
24
27
1
21
20
19
SCL
VDD
2
3
A2
TRIMA
START
COMP1
SMM205
4
18
17
16
15
A1
TRIM_CAPA
VMB
5
READY
6
A0
TRIMB
7
GND
TRIM_CAPB
13 14
12
8
9
10 11
Summit Microelectronics, Inc
2069 1.4 6/23/03
3
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
