SMM151/152
Preliminary Datasheet
I2C PROGRAMMING INFORMATION (CONTINUED)
S
T
S
T
A
A
R
T
Configuration
R
Master
Slave
Bus Address
Bus Address
Register Address
T
S
A
1
S
A
0
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
2
A
1
A
0
W
R
1
0
A
C
K
A
C
K
A
C
K
N
A
C
K
S
T
A
C
K
A
C
K
O
P
Master
Slave
Data (1)
Data (n)
D
7
D
D
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
D
4
D
3
D
D
1
D
0
6
5
5
2
Figure 16 - General Purpose Memory Read
S
T
S
T
A
R
T
Command and Status
Register Address
O
P
Master
Slave
Bus Address
Data
S
S
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
W
1
0
A
1
A
0
A
C
K
A
C
K
A
C
K
Figure 17 – Command and Status Register Write
S
T
S
T
A
R
T
A
Command and Status
R
Master
Slave
Bus Address
Bus Address
Register Address
T
S
A
1
S
A
0
S
A
3
S
A
2
S
S
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
2
A
1
A
0
W
R
1
0
A
1
A
0
A
C
K
A
C
K
A
C
K
N
A
C
K
S
T
A
C
K
A
C
K
O
P
Master
Slave
Data (1)
Data (n)
D
7
D
D
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
D
4
D
3
D
D
1
D
0
6
5
5
2
Figure 18 - Command and Status Register Read
Summit Microelectronics, Inc
2131 2.1 8/15/2008
21
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
