SMM151/152
PIN DESCRIPTIONS
Pin
Number
28
1
2
4
6
3, 9, 22, 27
Pin
Type
I/O
I
I
I
I
I/O
NC
I
CAP
O
I
I
I
I
PWR
O
PWR
PWR
GND
I
I
I
I
O
Pin Name
SDA
SCL
A2
A1
A0
GPIO0,1,2,3
NC
WP
CAPM+, -
TRIM
VM+
VM-
CS+
CS-
VREF
CAPC
VDD
VDD_CAP
GND
MUP
MDN
COMP1
COMP2
FAULT#
Pin Description
I
2
C Bi-directional data line
I
2
C clock input.
The address pins are biased either to VDD, GND or left floating. This allows
for a total of 21 distinct device addresses. When communicating with the
SMM151/2 over the 2-wire bus these pins provide a mechanism for
assigning a unique bus address.
SMM152: General purpose inputs/outputs.
SMM151: No Connect.
Programmable Write Protect active high/low input. When asserted, writes to
the configuration registers and general purpose EE are not allowed. The
WP input is internally tied to VDD with a 50KΩ resistor.
External capacitor inputs used to filter the VM+/VM- inputs, 0.22μF.
Output voltage used to control and/or margin converter voltages. Connect to
the converter trim input.
Voltage monitor input. Connect to the DC-DC converter positive sense line
or its +Vout pin.
Voltage monitor input. Connect to the DC-DC converter negative sense line
or its -Vout pin.
Current monitor input + side. Kelvin connect to the input supply side of the
current sense resistor.
Current monitor input - side. Kelvin connect to the load side of the current
sense resistor.
Internal reference voltage of 1.25V. Connect to GND through a 0.1uF
capacitor to improve noise immunity.
External capacitor input used to filter the CS+/CS- input. Typical value: 1uF.
Power supply of the part.
External capacitor input used to filter the internal VDD supply rail.
Ground of the part. The SMM151/2 ground pin should be connected to the
ground of the device under control or to a star point ground. PCB layout
should take into consideration ground drops.
Margin up command input. Asserted high. The MUP input is internally tied to
VDD with a 50KΩ resistor.
Margin down command input. Asserted high. The MDN input is internally
tied to VDD with a 50KΩ resistor.
COMP1 and COMP2 are high impedance inputs, each connected internally
to a comparator and compared against the internally programmable VREF
voltage. Each comparator can be independently programmed to monitor for
UV or OV. The monitor level is set externally with a resistive voltage
divider.
When either of the COMP1 or COMP2 inputs are in fault the open-drain
FAULT# output will be pulled low. A configuration option exists to disable
the FAULT# output while the device is margining.
8
10, 13
20
14
15
18
17
26
16
21
23
7
24
25
19
12
11
Summit Microelectronics, Inc
2131 3.0 1/20/2010
4
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
