SMM105
Preliminary Information
I2C PROGRAMMING INFORMATION
SERIAL INTERFACE
WRITE
Access to the configuration registers, general-purpose
memory and command and status registers is carried
out over an industry standard 2-wire serial interface
(I2C). SDA is a bi-directional data line and SCL is a
clock input. Data is clocked in on the rising edge of
SCL and clocked out on the falling edge of SCL. All
data transfers begin with the MSB. During data
transfers SDA must remain stable while SCL is high.
Data is transferred in 8-bit packets with an intervening
clock period in which an Acknowledge is provided by
Writing to the memory or a configuration register is
illustrated in Figures 9, 10, 11, 13, 14 and 16. A Start
condition followed by the address byte is provided by
the host; the SMM105 responds with an Acknowledge;
the host then responds by sending the memory
address pointer or configuration register address
pointer; the SMM105 responds with an acknowledge;
the host then clocks in one byte of data. For memory
and configuration register writes, up to 15 additional
bytes of data can be clocked in by the host to write to
consecutive addresses within the same page. After
the last byte is clocked in and the host receives an
Acknowledge, a Stop condition must be issued to
initiate the nonvolatile write operation.
the device receiving data. The SCL high period (tHIGH
)
is used for generating Start and Stop conditions that
precede and end most transactions on the serial bus.
A high-to-low transition of SDA while SCL is high is
considered a Start condition while a low-to-high
transition of SDA while SCL is high is considered a
Stop condition.
READ
The address pointer for the configuration registers,
memory, command and status registers and ADC
registers must be set before data can be read from the
SMM105. This is accomplished by issuing a dummy
write command, which is simply a write command that
is not followed by a Stop condition. The dummy write
command sets the address from which data is read.
After the dummy write command is issued, a Start
command followed by the address byte is sent from
the host. The host then waits for an Acknowledge and
then begins clocking data out of the slave device. The
first byte read is data from the address pointer set
during the dummy write command. Additional bytes
can be clocked out of consecutive addresses with the
host providing an Acknowledge after each byte. After
the data is read from the desired registers, the read
operation is terminated by the host holding SDA high
during the Acknowledge clock cycle and then issuing a
Stop condition. Refer to Figures 12, 15 and 17 for an
illustration of the read sequence.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
unique device addressing.
The address byte is
comprised of a 4-bit device type identifier (slave
address) and a 3-bit bus address. The remaining bit
indicates either a read or a write operation. Refer to
Table 1 for a description of the address bytes used by
the SMM105.
The device type identifier for the memory array, the
configuration registers and the command and status
registers are accessible with the same slave address.
It can be programmed to any four bit number 0000BIN
through 1111BIN
.
The bus address bits A[2:0] are hard wired only
though address pins 2, 4 and 6 (A2, A1 and A0). The
bus address accessed in the address byte of the serial
data stream must match the setting on the SMM105
address pins.
WRITE PROTECTION
The SMM105 powers up into a write protected mode.
Writing a code to the volatile write protection register
(write only) can disable the write protection. The write
protection register is located at address 42HEX. Writing
to the write protection register is shown in Figure 9.
Writing 0101BIN to bits [7:4] of the write protection
register allow writes to the general-purpose memory
while writing 0101BIN to bits [3:0] allow writes to the
configuration registers. The write protection can be re-
enabled by writing other codes (not 0101BIN) to the
write protection register.
Summit Microelectronics, Inc
2068 1.8 09/20/05
13
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
