Package and Pin descriptions
–
SML2120
PACKAGE AND PIN DESCRIPTIONS
Pin 1
ENA#
A1
A2
SDA
SCL
AM#
ALERT#
BIASMON
TEMPMON
POWERMON
VHI
VDD
EXT_TMP
VAPC
VSS
BIAS
VBURST
MPD
C1
C2
VDD
VLOW
VSS
VSS
THERMISTOR
VBRIDGE
ILU0
ILU1
Figure 4. 28-Pin QFN Package Pinout (top view)
PIN DESCRIPTIONS
PACKAGE AND PIN DESCRIPTIONS
PIN DESCRIPTIONS
PIN DESCRIPTIONS
Pin Number Pin Type
Pin Name
Description
1
2
3
4
5
6
I
I
I
I/O
I
I
ENA#
*
A1*
A2
*
SDA
*
SCL
*
AM#
*
Active low input enables the BIAS, ILU0 and ILU1 output currents.
The address pins are connected to either the VHI or VLOW pins to provide a
mechanism for assigning a unique I
2
C bus address to the SML2120.
Bi-directional I
2
C serial data pin
I
2
C serial clock input
AM# is an active low input, when asserted the SML2120 is placed in the Auto-
Monitor mode. AM# must be high for programming the Configuration registers
and the Lookup Tables, ILU0 and ILU1 and the general purpose E
2
PROM.
Active low, open-drain output indicates when one of the monitored inputs
exceeds its user-programmable high or low alert levels.
In dual-rail supply voltage systems, VLOW is tied to the system logic low
potential. It is a logic low reference for all pins marked with an asterisk (*).
VSS must be tied to the lowest system voltage potential.
7
8
9
10
11
O
PWR
PWR
PWR
I
ALERT#
*
VLOW
VSS
VSS
THERMISTOR
Connect a thermistor to this pin to provide an alternative source of temperature
sensing (see VBRIDGE description).
* See VLOW and VHI pin descriptions.
4
2066 6.3 1/22/04
Summit Microelectronics
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
