SMH4814
Preliminary Information
I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100/400kHz
Over recommended operating conditions, unless otherwise noted. All voltages are relative to VSS. See Figure 4
Timing Diagram.
100kHz
Min Typ
400kHz
Min Typ
Symbol Description
Conditions
Max
Max Units
fSCL
SCL Clock Frequency
0
100
0
400
KHz
tLOW
tHIGH
Clock Low Period
Clock High Period
4.7
4.0
1.3
0.6
µs
µs
Before New Transmission
- Note 1/
tBUF
Bus Free Time
4.7
1.3
µs
tSU:STA
tHD:STA
tSU:STO
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
4.7
4.0
4.7
0.6
0.6
0.6
µs
µs
µs
SCL low to valid
SDA (cycle n)
tAA
tDH
Clock Edge to Data Valid
Data Output Hold Time
0.2
0.2
3.5
0.2
0.2
0.9
µs
SCL low (cycle n+1)
µs
to SDA change
Note 1/
Note 1/
tR
tF
tSU:DAT
tHD:DAT
TI
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
Noise Filter SCL and SDA
Write Cycle Time
1000
300
1000
300
ns
ns
ns
ns
ns
ms
250
0
150
0
Noise suppression
Memory Array
100
100
tWR
5
5
Note: 1/ - Guaranteed by Design.
TIMING DIAGRAMS
tW R (For W rite Operation Only)
tHIGH
tLOW
tR
tF
SCL
tBUF
tHD:DAT
tSU:DAT
tSU:SDA
tSU:STO
tHD:SDA
SDA
(IN)
tAA
tDH
SDA
(OUT)
Figure 4 . Basic I2C serial interface timing diagram for the Bus Interface and Memory timing. The table above
lists the AC timing parameters. One bit of data is transferred during each clock pulse. Note that data must
remain stable when the clock is high.
Summit Microelectronics, Inc
2080 2.0 07/21/05
10