SMH4814
Preliminary Information
PIN DESCRIPTION (CONTINUED)
Pin No. Pin Type
QFN
Name
Description
Connect to the -48V 'A' feed using a series 100k resistor. The voltage on
this pin is compared with the voltage on the FEEDB pin internally by the
supply arbitration logic to determine which voltage will be used.
18
I
FEEDA
The DRAIN SENSE input monitors the voltage at the drain of the external
power MOSFET switch with respect to VSS. An internal 10µA source pulls
the DRAIN SENSE signal towards the 5V_CAP level. DRAIN SENSE must
be held below 2.5V to enable the PUPX outputs.
19
I
DRAIN
SENSE
External capacitor input used to filter the device’s internal operating supply.
20
21
O
O
5V_CAP
Also a hold Capacitor to sequence down and to filter any power glitches.
The VGATE_HS output activates an external power MOSFET switch. This
signal controls inrush current by modulating the gate of the Hot Swap
MOSFET device. It supplies a programmable current output which allows
easy adjustment of the MOSFET turn-on slew rate.
VGATE_HS
This pin controls the gate of the active FET on FEEDB.
This pin controls the gate of the active FET on FEEDA
This is the positive supply input. An internal shunt regulator limits the
voltage on this pin to approximately 12V with respect to VSS. A resistor
must be placed in series with the V12 pin to limit the regulator current (RD in
the application schematics).
22
23
24
O
O
PWR
VGATEB
VGATEA
V12
Active-high, logic level input that can be used to indicate when the converter
controlled by PUPD is fully powered. A hold-off timer allows the secondary
side (which is not powered up initially) to control shut down via an opto-
isolator. See Figures 5 and 6.
Active-high, logic level input that can be used to indicate when the converter
controlled by PUPC is fully powered. A hold-off timer allows the secondary
side (which is not powered up initially) to control shut down via an opto-
isolator. See Figures 5 and 6.
Active-high, logic level input that can be used to indicate when the converter
controlled by PUPB is fully powered. A hold-off timer allows the secondary
side (which is not powered up initially) to control shut down via an opto-
isolator. See Figures 5 and 6.
Active-high, logic level input that can be used to indicate when the converter
controlled by PUPA is fully powered. A hold-off timer allows the secondary
side (which is not powered up initially) to control shut down via an opto-
isolator. See Figures 5 and 6.
25
26
27
28
I
I
I
I
FBD
FBC
FBB
FBA
Summit Microelectronics, Inc
2080 2.0 07/21/05
5
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
