SMH4814
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S
T
S
T
A
Command
Register Address
R
O
P
Master
Slave
Bus Address
Data
T
A
2
A
1
D
7
D
6
D
5
D
D
3
D
2
D
1
D
0
1
0
0
1
0
W
0
0
0
0
0
0
0
0
4
A
C
K
A
C
K
A
C
K
Figure 31 – Command Register Write
S
T
S
T
A
R
T
A
Status
R
Master
Slave
Bus Address
Register Address
Bus Address
T
A
2
A
1
A
2
A
1
A
0
1
0
0
1
0
W
0
0
0
0
0
0
1
0
1
0
0
1
R
A
C
K
A
C
K
A
C
K
N
A
C
K
S
T
A
C
K
A
C
K
O
P
Master
Slave
Data (1)
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 32 - Status Register Read
Summit Microelectronics, Inc
2080 2.0 07/21/05
29