SMH4814
Preliminary Information
CONFIGURATION REGISTERS
Configuration Registers:
There are 20 user programmable configuration
registers in the SMH4814. The following tables
describe the configuration register bits in detail.
In cases where a timer is used, refer to the Timers
Table 3 for a description of the codes required for
each timeout selection.
Table 3 - Timers
All timers may be configured to one of the following sixteen choices:
Bit Code Timer (ms) Bit Code Timer (ms) Bit Code Timer (ms) Bit Code Timer (ms)
0000
0001
0010
0011
0.25
2
0100
0101
0110
0111
16
24
32
48
1000
1001
1010
1011
64
1100
1101
1110
1111
256
384
512
768
96
8
128
192
12
Register R00 – Initial Current Regulation and PD power-on delay.
Bits D[7:4] control the Initial Current Regulation Timer (defines the amount of time current regulation is allowed during
initial power-on). Bits D[3:0] control the Pin Detect delay (defines the time from when the PD’s are enabled and UV &
OV are valid until VGATE_HS is allowed to turn on)
Register R00
D7
1
D6
D5
0
D4
0
D3
X
D2
X
D1
X
D0
X
Action
0
Initial Current Regulation Timer – 64ms, See Table 3
X
X
X
1
0
0
0
Pin Detect Delay – 64ms, See Table 3
X
Register R01 –Sequence position.
Bits D[7:4] control the Time Slot 1 (time from FB high to second PUP allowed to go active). Bits D[3:0] control the
Time Slot 0, which is the time from when the FET is fully on to when the first PUP goes active.
Register R01
D7
1
D6
D5
D4
0
D3
X
D2
X
D1
X
D0
X
Action
Time Slot 1 - Time from FBX high to second PUPX
0
0
allowed to go active– 64ms, See Table 3
Time Slot 0 - Time from FBX high to first PUPX
allowed to go active – 64ms, See Table 3
X
X
X
X
1
0
0
0
Summit Microelectronics, Inc
2080 2.0 07/21/05
31
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
