SMH4814
Preliminary Information
CONFIGURATION REGISTERS (CONTINUED)
Register R02 –Time Slots.
Bits D[7:4] control the Time Slot 1 (time from FB high to second PUP allowed to go active). Bits D[3:0] control the
Time Slot 0 (time from FET fully on to first PUP allowed to go active). See timer table for bit codes.
Register R02
D7
1
D6
D5
D4
0
D3
X
D2
X
D1
X
D0
X
Action
Time Slot 3 - Time from FBX high to fourth PUPX
0
0
allowed to go active – 64ms, See Table 3
Time Slot 2 - Time from FBX high to third PUPX
allowed to go active – 64ms, See Table 3
X
X
X
X
1
0
0
0
Register R03 –Duty Cycle and Sequence Termination Timers.
Bits D[7:4] control the Duty Cycle Timer (restart time after fault; short circuit detect cycle time; multiply standard times
by 28X). Bits D[3:0] control the Sequence Termination Timer (defines time from PUP active until FB must go high).
Register R03
D7
1
D6
D5
D4
1
D3
X
D2
X
D1
X
D0
X
Action
Duty Cycle Timer – defines the time between when a
Fault occurs and the device attempts to restart the
power up sequence. Note that these times are
actually 28X of that listed in the table.
0
1
Sequence Termination Timer – time from when a
PUP is enabled until its corresponding FB input must
go high – 64ms, See Table 3
X
X
X
X
1
0
0
0
Register R04 –Current Regulation and UV/OV Filter Timers.
Bits D[7:4] control the Subsequent Current Regulation Timer (except for initial power on). Bits D[3:0] control the
UV/OV Filter Timer (when enabled).
Register R04
D7
1
D6
D5
D4
0
D3
X
D2
X
D1
X
D0
X
Action
Current Regulation Timer – defines the amount of
time that the FET can be held in the linear region to
regulate current to the load – 64ms, See Table 3
0
0
UV/OV Filter Time – defines the length of time that
an under or over voltage condition must be
X
X
X
X
1
0
0
0
sustained to trip the sensor – 64ms, See Table 3
Summit Microelectronics, Inc
2080 2.0 07/21/05
32
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
