SMH4811A
Preliminary
PIN DESCRIPTIONS
DRAIN SENSE (1)
The DRAIN SENSE input monitors the voltage at the drain
of the external power MOSFET switch with respect to V
SS
.
An internal 10µA source pulls the DRAIN SENSE signal
towards the 5V reference level. DRAIN SENSE must be
held below 2.5V to enable the PG outputs.
VGATE (2)
The VGATE output activates an external power MOSFET
switch. This signal supplies a constant current output
(100µA typical), which allows easy adjustment of the
MOSFET turn on slew rate.
EN/TS (3)
The Enable/Temperature Sense input is the master en-
able input. If EN/TS is less than 2.5V, VGATE will be
disabled. This pin has an internal 200kΩ pull-up to 5V.
PD1# and PD2# (4 & 5)
These are logic level active low inputs that can optionally
be employed to enable VGATE and the PG outputs when
they are at V
SS
. These pins each have an internal 50kΩ
pull-up to 5V.
FAULT# (6)
This is an open-drain, active-low output that indicates the
fault status of the device.
CBSENSE (7)
The circuit breaker sense input is used to detect over-
current conditions across an external, low value sense
resistor (R
S
) tied in series with the Power MOSFET. A
voltage drop of greater than 50mV across the resistor for
longer than t
CBD
will trip the circuit breaker. A program-
mable Quick-Trip™ sense point is also available.
UV (9)
The UV pin is used as an under-voltage supply monitor,
typically in conjunction with an external resistor ladder.
VGATE will be disabled if UV is less than 2.5V. Program-
mable internal hysteresis is available on the UV input,
adjustable in increments of 62.5mV. Also available is a
filter delay on the UV input.
OV (10)
The OV pin is used as an over-voltage supply monitor,
typically in conjunction with an external resistor ladder.
VGATE will be disabled if OV is greater than 2.5V. A filter
delay is available on the OV input.
5.0VREF & 2.5VREF (11 & 12)
These are precision 5V and 2.5V output reference volt-
ages that may be use to expand the logic input functions
on the SMH4803A. The reference outputs are with re-
spect to V
SS
.
ENPG (14)
This is an active high input that controls the PG# output.
When ENPG is pulled low the PG# output is immediately
placed in a high impedance state. This pin has an internal
50kΩ pull-up to 5V.
PG# (15)
The PG# pin is an open-drain, active-low output with no
internal pull-up resistor. It can be used to switch a load or
enable a DC/DC converter. PG# is enabled immediately
after VGATE reaches V
DD
– V
GT
and the DRAIN SENSE
voltage is less than 2.5V. Voltage on these pins cannot
exceed 12V, as referenced to V
SS.
V
DD
(16)
V
DD
is the positive supply connection. An internal shunt
regulator limits the voltage on this pin to approximately
12V with respect to VSS. A resistor must be placed in
series with the V
DD
pin to limit the regulator current (R
D
in
the application illustrations).
V
SS
(8)
V
SS
is connected to the negative side of the supply.
RECOMMENDED OPERATING CONDITIONS
Temperature
–40°C to 85°C.
SUMMIT MICROELECTRONICS, Inc.
2044 6.6
03/27/09
3
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
