SMH4044
Preliminary
V
V
&
TRIP
CC
HST_3V_MON
V
RVALID
LOCAL_PCI_RST#
BD_SEL1# &
BD_SEL2#
t
HSE
VGATE3 &
VGATE5
t
SLEW
V
OHVG
DRVREN#
CARD_3V_MON &
CARD_5V_MON
V
TRIP
t
PURST
HEALTHY#
SGNL_VLD#
2057 Fig01
Figure 1. Card Insertion Timing Diagram
Symbol
tVTPD
tVTR
tPRLPR
tSLEW
Parameter
Conditions
Min.
Typ.
Max.
5
Units
µs
VTRIP to power down delay
VTRIP to reset output delay
PCI_RST# to LOCAL_PCI_RST#
Slew rate
1
1
5
µs
0.1
1
µs
250
30
V/s
ms
ms
ms
ms
ms
ms
ms
ms
s
25ms configuration
50ms configuration
100ms configuration
200ms configuration
25ms configuration
50ms configuration
100ms configuration
200ms configuration
0.8s configuration
1.6s configuration
3.2s configuration
20
40
25
50
60
tHSE
BD_SEL# to power on delay
80
100
200
25
120
240
30
160
20
40
50
60
tPURST
RESET pulse width
80
100
200
0.8
1.6
3.2
120
240
0.96
1.92
3.84
40
160
0.64
1.28
2.56
tWD
Watchdog timer duration
s
s
tGLITCH
tOCF
tOCVG
tCBTC
Glitch rejection pulse width
Overcurrent to FAULT# output
Overcurrent to gate off
ns
1
1
µs
µs
Circuit breaker time constant
Operating
16
µs
2057 Table01
Table 1. Card Insertion Timing
10
SUMMIT MICROELECTRONICS, Inc.
2057 1.x 8/16/01
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
