SMH4042
READ OPERATIONS
The SMH4042 automatically increments the address for
subsequent data words. After the receipt of each word,
the low order address bits are internally incremented by
one. The high order bits of the address byte remain
constant. Should the master transmit more than 16 bytes,
prior to generating the STOP condition, the address
counter will “roll over,” and the previously written data will
be overwritten. As with the byte-write operation, all inputs
are disabled during the internal write cycle. Refer to
Figure 5 for the address, ACKnowledge and data transfer
sequence.
Read operations are initiated with the R/W bit of the
identification field set to “1.” There are two different read
options:
1. Current Address Byte Read
2. Random Address Byte Read
Current Address Read
The SMH4042 contains an internal address counter
which maintains the address of the last word accessed,
incremented by one. If the last address accessed (either
a read or write) was to address location n, the next read
operation would access data from address location n+1
and increment the current address pointer. When the
SMH4042 receives the slave address field with the R/W
bit set to “1,” it issues an acknowledge and transmits the
8-bit word stored at address location n+1. The current
address byte read operation only accesses a single byte
of data. The master does not acknowledge the transfer,
but does generate a stop condition. At this point, the
SMH4042 discontinues data transmission.
Acknowledge Polling
When the SMH4042 is performing an internal WRITE
operation, it will ignore any new START conditions. Since
the device will only return an acknowledge after it accepts
the START, the part can be continuously queried until an
acknowledgeisissued, indicatingthattheinternalWRITE
cycle is complete. See the flow diagram below for the
proper sequence of operations for polling.
Write Cycle
In Progress
Random Address Read
Random address read operations allow the master to
access any memory location in a random fashion. This
operation involves a two-step process. First, the master
issuesawritecommandwhichincludesthestartcondition
andtheslaveaddressfield(withtheR/WbitsettoWRITE)
followed by the address of the word it is to read. This
procedure sets the internal address counter of the
SMH4042 to the desired address. After the word address
acknowledgeisreceivedbythemaster, themasterimme-
diately reissues a start condition followed by another
slave address field with the R/W bit set to READ. The
SMH4042 will respond with an ac-knowledge and then
transmit the 8-data bits stored at the addressed location.
At this point, the master does not acknowledge the
transmission but does generate the stop condition. The
SMH4042 discontinues data transmission and reverts to
its standby power mode.
Issue Start
Issue Stop
Issue Slave
Address and
R/W = 0
ACK
Returned?
Next
Operation
a Write?
Issue Stop
Issue
Address
Proceed
With
Write
Await
Next
Command
2037 ILL16.0
2037 8.0 8/8/00
13
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
