SMH4042A
GND(14)
LOCAL_PCI_RST#(9)
Powersupplyreturnline. Groundshouldbeappliedatthe
same time as early power.
An open-drain active-low output. It is used to reset the
backendcircuitryontheadd-incard. Itisactivewhenever
the card-side monitor inputs are below their respective
VTRIP levels. It may also be driven low by a low input on
the PCI_RST# pin.
BD_SEL1#, BD_SEL2# (13, 12)
These are active low TTL level inputs with internal pull-
ups to VCC. When pulled low they indicate full board
insertion. On the host side the signals should be directly LOCAL_PCI_RST (20)
tied to ground. In a “High Availability” application these
An open-drain (PFET) active-high output. It operates in
inputs can be the last pins to mate with the backplane.
Alternatively, they can be actively driven by the host, or
beconnectedtoswitchesinterfacedtotheboardejectors,
or any combination. Regardless, both inputs must be low
before the SMH4042A will begin to turn on the backend
voltage.
parallel with LOCAL_PCI_RST#, providing an active high
reset signal which is required by many 8051 style MCUs.
It is active whenever the card-side monitor inputs are
below their respective VTRIP levels. It may also be driven
active by a low input on the PCI_RST# pin.
SGNL_VLD# (16)
DRVREN# (2)
An open-drain, active-low output that indicates card side
power is valid and the internal card side PCI_RST# timer
has timed out.
An open-drain, active-low output that indicates the status
of the 3 volt and 5 volt high side driver outputs (VGATE5
and VGATE3). This signal may also be used as a
switching signal for the 12 volt supply.
VGATE3 (22)
FAULT# (4)
A slew rate limited high side driver output for the 3.3V
externalpowerFETgate. Theoutput-voltageisgenerated
by an on-board charge pump.
An open-drain, active-low output. It will be driven low
whenever an over-current condition is detected. It will be
reset at the same time that the VGATE outputs are turned VGATE5 (27)
backonafteraresetfromthehostonthePWR_ENsignal.
A slew rate limited high side driver output for the 5V
HEALTHY# (15)
externalpowerFETgate. Theoutputvoltageisgenerated
by an on-board charge pump.
An open-drain, active-low output indicating card side
power inputs are above their reset trip levels.
1VREF (5)
This output provides a 1V reference for pre-charging the
bus signal pins. Implementing a simple unity-gain ampli-
fier circuit will allow pre-charging a large number of pins.
RECOMMENDEDOPERATINGCONDITIONS*
ABSOLUTE MAXIMUM RATINGS*
TemperatureUnderBias......................... –55°Cto125°C
StorageTemperature .............................. –65°Cto150°C
LeadSolderTemperature(10secs) ..................... 300°C
TemperatureRange(Industrial)...……....-40°Cto+85°C
(Commercial)...……....-5° C to +70°C
Supply Voltage………………….....….………2.7V to 5.5V
Package Thermal Resistance (θ JA)
Terminal Voltage with Respect to GND:
CARD_3V_MON,CARD_5V_MON,
28 Lead SOIC/SSOP...…………………………80oC/W
Moisture Classification Level 1 (MSL 1) per J-STD- 020
HST_3V_MON,SGNL_VLD#,HEALTHY#,
LOCAL_PCI_RET#,V ........................................ 7V
CC
VGATE3,VGATE5,DRVREN# .................. 16V
RELIABILITYCHARACTERISTICS
DataRetention……………………………..…..100Years
Endurance……………………….……….100,000Cycles
RESET ............................................ V + 0.7V
CC
All Others ........................................ V + 0.7V
CC
Junction Temperature..........................................150°C
Note * - The device is not guaranteed to function outside its operating
rating. Stresses listed under Absolute Maximum Ratings may cause
permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions
outside those listed in the operational sections of this specification is
not implied. Exposure to any absolute maximum rating for extended
ESDRatingperJEDEC……………………………..2000V
Latch-Up testing per JEDEC………………......+/- 100mA
periods may affect device performance and reliability.
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
4
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
