SMH4042A
APPLICATIONS
DESIGNCONSIDERATIONSFORACOMPACTPCI
BOARD
Figure 11 is a generic representation of a CompactPCI
board and it illustrates how the SMH4042A is the key
component in the board insertion/removal process. The
illustrations that follow show in more detail how the
various blocks interface to the SMH4042A.
Backend Power Plane
and Logic
P2
Current
sense
resistors
Backend Power
SwitchingCircuits
Precharge
Circuit
V(I/O)
eP
SGNL_VLD
CBI_3
1Vref
VCC5
ENUM#
CBI_5
V(I/O)
5V
HST_3V_MON
3.3V
CARD_3V_MON
CARD_5V_MON
Current
limiting
resistors
V(I/O)
V(I/O)
GND
GND
VGATE3
VGATE5
BD_SEL#
BD_SEL2#
GND
Capacitance
4.7µf each
eP
V(I/O)
GND
GND
GND
LOCAL_PCI_RST#
BD_SEL1#
RESET
3.3V
PCI_RST#
HEALTHY#
GND, PCI_RST#
HEALTHY#
5V
5V
SMH4042A
+12V, -12V
P1
2070 Fig11
Figure 11. Diagram of Typical CompactPCI Board
limitingresistors. Notetheplacementofthesense(shunt)
resistors. They are in series with the power FETs and no
voltage drop will be detected across the resistor until
VGATE is applied to the power FETs. The sense resistor
values are determined by dividing 50mV by the current
specification for that supply.
Power Busses
It is important in the design of the board to ensure the
backend logic is isolated from the power control circuits
and other early power circuits such as FPGAs and the I/
O interface circuits. In Figure 12 the early power busses
for 5V and 3V have series current limiting resistors.
These values should be calculated so as to limit the in-
rush current that will initially charge the capacitive load
of the early power circuits. As the card is inserted further,
the medium length pins engage and short out the current
It should be noted that there is an inherent delay from
VGATE5 turning on to VGATE3 turning on. The typical
delay is illustrated in Figure 13.
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
16
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
