SMH4042A
DEVICE OPERATION
andgroundorbyinjectingcurrentintotheISLEWinput. All
circuitry on the card is held in a reset condition until the 5V
(or 3.3V) supply is stable and the reset interval timer has
timed out the 150ms reset time. At this point, the reset
signals are de-asserted, and proper operation of the card
commences. See Figure 1, Table 1, and Flow Chart 1.
Power-UpSequence
TheSMH4042Aisanintegratedpowercontrollerforanyhot
swappable add-in card. It provides all the signals and
control functions to be compatible with CompactPCI Hot
Swap requirements for basic hot swap systems, full hot
swap boards, and high availability systems.
The SMH4042A will monitor the card’s backend voltages.
Once they are at or above the card VTRIP levels the
SMH4042A will drive the HEALTHY# output.
Insertion Process
As the add-in board is inserted into the backplane,
physical connections are made with the chassis in order
to properly discharge any voltage potentials to ground.
The board will first contact the long pins on the backplane
that provide early power (5V, 3.3V and ground). Depend-
ing upon the board configuration, early power should be
routedtotheVCC pinoftheSMH4042A. Assoonaspower
isappliedtheSMH4042Awillasserttheresetoutputstothe
backend circuits, turn off the VGATE3 and VGATE5
outputs (disabling the external power FETs) and assert
1VREF. Thissignalcanbeusedtopre-chargetheI/Opins
before they begin to mate with the bus signals. The open
collector HEALTHY# output will be de-asserted. It should
be actively pulled high by an external pull-up resistor
(minimum 10kΩ).
Card Removal Process
The card removal process operates in the opposite
sequence. For non-high-availability cards the action of
card removal disconnects the BD_SEL# (short pins) from
ground and the SMH4042A will instantly shutdown the
VGATE outputs, change the HEALTHY# status, and
assert the LOCAL_PCI_RST# output.
Because connectors to the host backplane employ stag-
geredpins,powerwillstillbeappliedtotheSMH4042Aand
the I/O interface circuits. The LOCAL_PCI_RST# signal
will place the interface circuits into a high impedance
condition. The pre-charge voltage will be applied to the
I/Os enabling a graceful disengagement from the active
bus. Once the I/O pins are free of the backplane, power
canberemovedfromtheSMH4042Aandotherearlypower
devices by releasing the long pins.
The next pins to mate are the I/Os, and the balance of the
power pins if they are not already mated. The I/Os will
have been pre-charged by the 1VREF output.
The BD_SEL# pins are the last inputs to be driven to their
true state. In most systems these will most likely be
driven to ground when the short pins are mated. This
would indicate the card is fully inserted and the power-up
sequence can begin. If, however, the design is based on
high availability requirements, the two pins can be ac-
tively driven by the host or combined with a switch input
indicating the ejector handles are fully engaged.
The removal process is slightly different for a high-
availability system. As the ejector handle is rotated the
ejectorswitchwillopen, causingachangeofstatethatwill
activate the ENUM# signal to the host. In response to this
notification the host will de-assert a hardware controlled
BD_SEL# signal. This action will turn on an indicator LED
onthecard,notifyingtheoperatoritisnowsafetoproceed
withtheremovalofthecard. Thesequencewillthenfollow
that outlined for the non-high-availability removal pro-
cess.
Sequencing
Once the proper card insertion has been assured the
SMH4042A will check the status of the Power Enable
signalfromthehost. Thisinputcanbeusedtopowerdown
individual cards on the bus via software control. It must
by held high in order for the SMH4042A to enable power
sequencing to the card.
Power Configurations
The SMH4042A can be used in 5V-only, 3.3V-only and
mixed voltage systems. For systems with a single power
supply, connect VCC and HST_3V_MON together to the
bus power line. Also connect CARD_3V_MON and
CARD_5V_MONtogethertothecardsidepower. Nowthe
state of VSEL determines the reset level that will be used
Whentheseconditionshavebeenmet,theSMH4042Awill
drive the VGATE3 and VGATE5 outputs to turn on the
external 3 volt and 5 volt power FETs. The slew rate of
these outputs is controlled to a slew rate of 250V/s.
Different slew rates can be accommodated by either
addinganadditionalcapacitorbetweentheMOSFETgate
to signal valid power. For 3.3V systems tie VSEL to VCC
for 5V systems tie VSEL to ground.
,
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
6
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
