SMH4042A
BUSINTERFACE
GENERAL DESCRIPTION
Check Table 2 for the value of fSCL. The SDA line must
The I2C bus is a two-way, two-line serial communication be connected to a positive supply by a pull-up resistor
between different integrated circuits. The two lines are: located on the bus. Summit parts have a Schmitt input on
a serial Data line (SDA) and a serial Clock line (SCL). All both lines. See Figure 5 and Table 2 for waveforms and
Summit Microelectronics parts support a 100kHz clock timing on the bus. One bit of Data is transferred during
rate, and some support the alternative 400kHz clock. each Clock pulse. The Data must remain stable when the
Clock is high.
t
t
LOW
HIGH
t
t
R
F
SCL
t
t
t
t
SU:STO
t
HD:DAT
SU:SDA
SU:DAT
HD:SDA
t
BUF
SDA In
t
t
AA
DH
SDA Out
2070 Fig05
Figure 5. I2C Timing Diagram
Symbol
Parameter
Conditions
Min. Typ. Max. Units
f
SCL clock frequency
Clock low period
0
100
kHz
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ms
SCL
t
4.7
4.0
4.7
4.7
4.0
4.7
0.2
LOW
t
Clock high period
HIGH
t
BUF
Bus free time (1)
Before new transmission
t
Start condition setup time
Start condition hold time
Stop condition setup time
SU:STA
t
HD:STA
t
SU:STO
t
AA
Clock edge to valid output SCL low to valid SDA (cycle n)
3.5
t
DH
Data Out hold time
SCL low (cycle n+1) to SDA change 0.2
t
R
SCL and SDA rise time (1)
SCL and SDA fall time (1)
Data In setup time
1000
300
t
F
t
250
SU:DAT
t
Data In hold time
0
HD:DAT
TI
Noise filter SCL and SDA
Write cycle time
Noise suppression
100
t
WR
5
Note1-GuaranteedbyDesign
2037 Table02 2.0
Table 2. I2C AC Operating Characteristics
SUMMIT MICROELECTRONICS, Inc.
2070 9.1 5/27/03
11
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
