SMH4042A
Start and Stop Conditions
3
9
1
2
8
SCL
BothDataandClocklinesremainhighwhenthebusisnot
busy. Datatransferbetweendevicesmaybeinitiatedwith
aStartconditiononlywhenSCLandSDAarehigh. Ahigh-
to-lowtransitionoftheDatalinewhiletheClocklineishigh
is defined as a Start condition. A low-to-high transition of
the Data line while the Clock line is high is defined as a
Stop condition. See Figure 6.
SDA
Trans
SDA
Rec
ACK
2070 Fig07
Figure 7. Acknowledge Timing
START
Condition
STOP
Condition
leave the Data line high for a NACK. This will cause the
Summit part to stop sending data, and the Master will
issue a Stop on the clock pulse following the NACK.
SCL
InthecaseofaWritetoaSummitparttheMasterwillsend
aStopontheclockpulseafterthelastAcknowledge. This
will indicate to the Summit part that it should begin its
internal non-volatile write cycle.
SDA In
2070 Fig06
Figure 6. I2C Start and Stop Timing
Basic Read and Write
Protocol
The first byte from a Master is always made up of a seven
bitSlaveaddressandtheRead/Writebit. TheR/Wbittells
the Slave whether the Master is reading data from the bus
or writing data to the bus (1 = Read, 0 = Write). The first
four of the seven address bits are called the Device Type
Identifier(DTI). TheDTIfortheSMH4042Ais1010BIN. The
next two bits are used to select one-of-four possible
devices on the bus. The next bit is the block select bit.
TheSMH4042AwillissueanAcknowledgeafterrecogniz-
ing a Start condition and its DTI.
The protocol defines any device that sends data onto the
bus as a Transmitter, and any device that receives data
as a Receiver. The device controlling data transmission
is called the Master, and the controlled device is called
the Slave. In all cases the Summit Microelectronic
devices are Slave devices, since they never initiate any
data transfers.
Acknowledge
In the Read mode the SMH4042A transmits eight bits of
Data is always transferred in 8-Bit bytes. Acknowledge
(ACK) is used to indicate a successful data transfer. The data, then releases the SDA line, and monitors the line for
Transmitting device will release the bus after transmitting an Acknowledge signal. If an Acknowledge is detected,
and no Stop condition is generated by the Master, the
SMH4042A will continue to transmit data. If an Acknowl-
edgeisnotdetected(NACK),theSMH4042Awillterminate
eight bits. During the ninth clock cycle the Receiver will
pull the SDA line low to Acknowledge that it received the
eight bits of data (See Figure 7). The termination of a
Master Read sequence is indicated by a non-Acknowl- further data transmission. See Figure 9.
edge (NACK), where the Master will leave the Data line
In the Write mode the SMH4042A receives eight bits of
data, then generates an Acknowledge signal. It will
high.
In the case of a Read from a Summit part, when the last continue to generate ACKs until a Stop condition is
byte has been transferred to the Master, the Master will generated by the Master. See Figure 10.
SCL
SDA
3
1
5
x
8
9
1
1
2
0
4
0
6
x
7
x
R/W
ACK
2070 Fig08
Figure 8. Typical Master Address Byte Transmission
2070 9.1 5/27/03
SUMMIT MICROELECTRONICS, Inc.
12
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
