SMD1102 / 1103 / 1113
DEVICE OPERATION
The SMD1102, SMD1103 and SMD1113 Data Acquisition
Systems (DAS) are each comprised of: an analog input
multiplexer, sample-and-hold circuit, 10-Bit successive
approximation Analog-to-Digital (A/D) Converter, and
nonvolatile EEPROM memory to store upper and lower
alarm-limits for each input channel. The user programs
the alarm limits via the industry-standard I
2
C interface. An
SMB
ALERT
#
interrupt output signals if any of the analog
inputs move outside these limits.
DAS Modes of Operation
The SMD1102/1103/1113 have four user-selectable
modes of operation. These modes are: a single conver-
sion of one channel, successive conversions on the same
channel, sequential conversions on all three channels, or
autonomous conversions of the same or all channels.
Sample-and-Hold Operation
The channel switching and sampling architecture of the A/
D’s comparator is illustrated in the equivalent input circuit
diagram in Figure 1. During acquisition the selected
channel charges a capacitor in the sample-and-hold cir-
cuit. The acquisition interval spans the Acknowledge
period following the command byte and ends on the rising
edge of the next clock. At the end of the acquisition phase
the analog input is disconnected, retaining charge on the
hold capacitor as a sample of the signal.
Sample
& Hold
+
–
The next bit in the addressing sequence is the EEPROM/
Conversion (E/C) bit; when set to zero the device is
instructed to perform an A/D conversion, and when set to
logic one the EEPROM limit register will be addressed.
See Table 1A.
The next two bits are the channel select bits. Auto-
increment is enabled if the channel select bits are set to
11
BIN
and the conversion bit is set to zero. In the auto-
increment mode conversions are performed on succes-
sive channels, starting with channel 0. After channel 2 is
converted (channel 1 on the SMD1102) the address will
wrap around to channel 0. See Table 1B.
The last bit is the Read/Monitor bit. When the bit is set
to logic one, data can be read from a conversion or from
one of the EEPROM limit registers, depending on the state
of the EEPROM/Conversion bit. When the bit is logic zero
either the auto-monitor mode is entered or the EEPROM
limit register is programmed, again depending on the state
of the EEPROM/Conversion bit. See Table 1C.
DB7 DB6
A2
or
1*
A1
or
0*
DB5
A0
0
or
0*
1
1
DB4
DB3
E/C
Device Type Identifier
Function
Perform A/D con-
version on selected
channel(s)
Address EEPROM
limit register
2033 Table01A
Buffer
Analog In
*
Denotes SMD 1102 & SMD1103. Ax bits are for the SMD1113.
Table 1A. Address Byte — EEPROM/Conversion
DAC
DB7 DB6 DB5 DB4 DB2 DB1
SAR
SDA
Device Type Identifier CH1 CH0
0
2033 Fig01 2.0
Function
Channel 0
selected
Channel 1
selected
Channel 2
selected
Auto-increment if
E/C = 0
2033 Table01B
0
1
0
1
A2
A1
or
0*
A0
0
or
0*
1
1
1
Figure 1. Sample/Hold and SAR
Addressing and Command Sequence
All operations of the DAS are preceded first by the start
condition and then by the addressing command se-
quence. For the SMD1102 & SMD1103 this is 1001
BIN.
For
the SMD1113 it is the binary values of A2, A1, A0, and a
one — a four bit number.
or
1*
*
Denotes SMD 1102 & SMD1103. Ax bits are for the SMD1113.
Table 1B. Address Byte — Channel Select
SUMMIT MICROELECTRONICS, Inc.
2033 8.1 10/04/01
5
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
