SMB214A/B/C
I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100 kHz
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
100kHz
Symbol
Description
Conditions
Min
0
4.7
4.0
Typ
Max Units
fSCL
TLOW
THIGH
SCL clock frequency
Clock low period
Clock high period
100
kHz
µs
µs
Before new transmission –
Note 5
tBUF
Bus free time
4.7
µs
tSU:STA
tHD:STA
tSU:STO
Start condition setup time
Start condition hold time
Stop condition setup time
4.7
4.0
4.7
µs
µs
µs
SCL low to valid SDA (cycle
n)
tAA
tDH
Clock edge to data valid
Data output hold time
0.2
0.2
3.5
µs
SCL low (cycle n+1) to SDA
µs
change
Note 5
Note 5
tR
tF
SCL and SDA rise time
SCL and SDA fall time
Data in setup time
1000
300
ns
ns
ns
ns
ns
ms
ms
tSU:DAT
tHD:DAT
TI
tWR_CONFIG
tWR_EE
250
0
Data in hold time
Noise filter SCL and SDA
Write cycle time config
Write cycle time EE
Noise suppression
Configuration registers
Memory array
136
10
5
Note 5: Guaranteed by Design.
TIMING DIAGRAMS
tWR (For Write Operation Only)
tHIGH
tLOW
tR
tF
SCL
tBUF
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
tHD:STA
SDA (IN)
tAA
tDH
SDA (OUT)
Figure 4 – I2C timing diagram
Summit Microelectronics, Inc
2128 2.0 6/20/2008
12
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
