SMB113A/B/SMB117/A
Preliminary Information
INTERNAL BLOCK DIAGRAM
COMP2_CH[0,1,2,3]
VM_CH[0,1,2,3]
100k
–
+
OA
+
–
CLAMP
MAX LIMIT
LOW LIMIT
DUTY
CYCLE
LIMIT
OSC
Fixed 250/400/
800/1000kHz
HVSUP[0,1,2,3]
Channel 0,1,2,3
Synchronous buck
PWM Converter
HSDRV[0,1,2,3]
I
2
C/SMBUS
SDA
SCL
COMP1_CH[0,1,2,3]
VREF
LEVEL
SHIFTER
DIGITAL TO
ANALOG
CONVERTER
DEADTIME
+
–
GLITCH
FILTER
OVER VOLTAGE
DETECTION
LSDRV[0,1,2,3]
SEQUENCING
AND
MONITORING
LOGIC
ENABLE
PWREN0
+
–
VREF
VREF
GLITCH
FILTER
UNDER VOLTAGE
DETECTION
VBATT
VDDCAP
GND
BANDGAP
VDD_CAP
2.5V
REGULATOR
+
–
UV2
D
Q
LEVEL
SHIFTER
VREF
+
–
UV1
Figure 3 –SMB113A/B and SMB117/A internal block diagram. Programmable functional blocks include: level
shifters, digital to analog converter and the VM_CH[0,1,2,3] voltage dividers.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
4
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
