SMB113A/B/SMB117/A
Preliminary Information
INTERNAL BLOCK DIAGRAM
COMP2_CH[0,1,2,3]
VM_CH[0,1,2,3]
HVSUP[0,1,2,3]
Channel 0,1,2,3
HSDRV[0,1,2,3]
Synchronous buck
PWM Converter
100k
z
–
+
DUTY
CYCLE
LIMIT
+
–
OA
z
z
I2C/SMBUS
SDA
SCL
DEADTIME
MAX LIMIT
LOW LIMIT
CLAMP
OSC
Fixed 250/400/
800/1000kHz
COMP1_CH[0,1,2,3]
+
–
z
z
OVER VOLTAGE
DETECTION
GLITCH
FILTER
LSDRV[0,1,2,3]
PWREN0
VREF
LEVEL
SEQUENCING
AND
SHIFTER
DIGITAL TO
ANALOG
+
–
MONITORING
LOGIC
UNDER VOLTAGE
DETECTION
GLITCH
FILTER
CONVERTER
VREF
ENABLE
GND
VBATT
VREF
BANDGAP
VDDCAP
z
z
+
–
VDD_CAP
UV2
2.5V
z
REGULATOR
z
D
Q
+
–
LEVEL
UV1
z
SHIFTER
VREF
Figure 3 –SMB113A/B and SMB117/A internal block diagram. Programmable functional blocks include: level
shifters, digital to analog converter and the VM_CH[0,1,2,3] voltage dividers.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
4
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
