S93WD662/S93WD663
PIN CAPACITANCE
Symbol
C
OUT(1)
C
IN(1)
Test
OUTPUT CAPACITANCE (DO)
INPUT CAPACITANCE (CS, SK, DI, ORG)
Max.
5
5
Units
pF
pF
Conditions
V
OUT
=OV
V
IN
=OV
2013 PGM T4 1.0
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
A.C. CHARACTERISTICS
(over recommended operating conditions unless otherwise specified)
Limits
V
CC
=2.7V-4.5V V
CC
=4.5V-5.5V
SYMBOL PARAMETER
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ(1)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.5
0.5
0.5
0.5
500
DC
Min.
100
0
200
200
0.5
0.5
200
10
0.25
0.25
0.25
0.25
1000
Max.
Min.
50
0
100
100
0.25
0.25
100
10
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
KHZ
2013 PGM T6 1.0
Test
Max. UNITS Conditions
V
IL
= 0.45V
V
IH
= 2.4V
C
L
= 100pF
V
OL
= 0.8V
V
OH
= 2.0v
C
L
= 100pF
C
L
= 100pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
2013 2.1 8/2/00
8
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
