S93462/S93463
SK
CS
STATUS VERIFY
t CS
STANDBY
DI
1
0
0
1
0
t SV
t HZ
BUSY
t EW
2021 ILL 8 1.0
DO
HIGH-Z
READY
HIGH-Z
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
t CS
STANDBY
DI
1
0
0
0
1
DN
DO
t SV
t HZ
BUSY
t EW
READY
HIGH-Z
DO
Figure 7. WRAL Instruction Timing
2021 ILL 10 1.0
INSTRUCTION SET
Instruction
READ
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Start
Bit
1
1
1
1
1
1
1
Opcode
10
11
01
00
00
00
00
Address
x8
x16
A6–A0
A6–A0
A6–A0
11xxxxx
00xxxxx
10xxxxx
01xxxxx
A5–A0
A5–A0
A5–A0
11xxxx
00xxxx
10xxxx
01xxxx
D7–D0
D15–D0
D7–D0
D15–D0
Data
x8
Comments
x16
Read Address AN–A0
Clear Address AN–A0
Write Address AN–A0
Write Enable
Write Disable
Clear All Addresses
Write All Addresses
2021 PGM T5 1.1
6
2021 4.2 1/23/01
Summit Microelectronics, Inc.