S93462/S93463
SK
CS
DI
STANDBY
STATUS VERIFY
t
CS
1
0
0
1
0
t
t
SV
HZ
HIGH-Z
DO
BUSY
READY
HIGH-Z
t
EW
2021 ILL 8 1.0
Figure 6. ERAL Instruction Timing
SK
CS
DI
STANDBY
STATUS VERIFY
t
CS
D
D
1
0
0
0
1
N
O
t
t
HZ
SV
DO
BUSY
READY
HIGH-Z
t
EW
2021 ILL 10 1.0
Figure 7. WRAL Instruction Timing
INSTRUCTION SET
Instruction
Start
Bit
Opcode
Address
x8
Data
x8
Comments
x16
x16
READ
ERASE
WRITE
EWEN
EWDS
ERAL
1
10
11
01
00
00
00
00
A6–A0
A6–A0
A5–A0
A5–A0
A5–A0
11xxxx
00xxxx
10xxxx
01xxxx
Read Address AN–A0
Clear Address AN–A0
Write Address AN–A0
Write Enable
1
1
A6–A0
D7–D0
D7–D0
D15–D0
D15–D0
1
11xxxxx
00xxxxx
10xxxxx
01xxxxx
1
Write Disable
1
Clear All Addresses
WRAL
1
Write All Addresses
2021 PGM T5 1.1
6
2021 4.2 1/23/01
Summit Microelectronics, Inc.
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
