S4242/S42WD42/S4261/S42WD61
PIN CONFIGURATIONS
8-Pin PDIP
or 8-Pin SOIC
PIN NAMES
Symbol
VLOW
Pin
1
Description
Open drain output, active when
VSENSE < 1.24V
#
RESET#
VSENSE
2
Active low I/O
1
2
3
4
8
7
6
5
V
CC
RESET
SCL
SDA
V
#
LOW
RESET#
2nd monitor voltage input.VLOW
output when < 1.24V
#
3
V
SENSE
GND
GND
SDA
4
5
6
7
8
Analog & digital ground
Serial memory I/O data line
Serial memory clock
Active high I/O
2025 T PCon 2.0
SCL
RESET
VCC
Supply voltage
V
= 3.0V or 5.0V
PB_RST#
CC
VBAT TO
REGULATOR
INTO (P1.5)
S42xxx
8051 Type
MCU
RST
SCL (P0.0)
SDA (P0.1)
V
#
V
CC
LOW
RESET#
RESET
SCL
V
BAT
V
GND
SENSE
TRIP
SDA
2
I C Peripheral
RESET#
SCL
SDA
2025 T fig06 2.0
FIGURE 6. TYPICAL SYSTEM CONFIGURATION USING A PUSH BUTTON RESET AND BATTERY MONITOR CIRCUIT
V
= 5.0V ±10%
CC
SECOND CARD
VOLTAGE
3.0V ±5%
General
Purpose
MCU
S42xxx
V
#
V
CC
LOW
RESET#
RESET
SCL
SCL
SDA
V
GND
SENSE
SDA
RESET#
2
I C Peripheral
RESET#
SCL
SDA
2025 T fig07 2.0
FIGURE 7. TYPICAL SYSTEM CONFIGURATION FOR DUAL RESET WITH VCC MONITOR AND 3.3VOLT MONITOR
2025 6.0 4/17/00
6
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
