S4242/S42WD42/S4261/S42WD61
PIN CONFIGURATIONS
8-Pin PDIP
or 8-Pin SOIC
PIN NAMES
Symbol
V
LOW
#
Pin
1
2
3
4
5
6
7
8
Description
Open drain output, active when
V
SENSE
< 1.24V
Active low I/O
2nd monitor voltage input.V
LOW
#
output when < 1.24V
Analog & digital ground
Serial memory I/O data line
Serial memory clock
Active high I/O
Supply voltage
VLOW#
RESET#
VSENSE
GND
1
2
3
4
8
7
6
5
VCC
RESET
SCL
SDA
RESET#
V
SENSE
GND
SDA
SCL
RESET
V
CC
2025 T PCon 2.0
PB_RST#
VCC = 3.0V or 5.0V
VBAT TO
REGULATOR
INTO (P1.5)
S42xxx
VBAT
TRIP
VLOW#
RESET#
VSENSE
GND
VCC
RESET
SCL
SDA
8051 Type
MCU
RST
SCL (P0.0)
SDA (P0.1)
I
2
C Peripheral
RESET#
SCL
SDA
2025 T fig06 2.0
FIGURE 6. TYPICAL SYSTEM CONFIGURATION USING A PUSH BUTTON RESET AND BATTERY MONITOR CIRCUIT
VCC = 5.0V ±10%
SECOND CARD
VOLTAGE
3.0V ±5%
S42xxx
VLOW#
RESET#
VSENSE
GND
VCC
RESET
SCL
SDA
General
Purpose
MCU
SCL
SDA
RESET#
I
2
C Peripheral
RESET#
SCL
SDA
2025 T fig07 2.0
FIGURE 7. TYPICAL SYSTEM CONFIGURATION FOR DUAL RESET WITH V
CC
MONITOR AND 3.3VOLT MONITOR
2025 6.0 4/17/00
6
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
