S4242/S42WD42/S4261/S42WD61
PIN DESCRIPTIONS
Serial Clock (SCL)
- The SCL input is used to clock data
into and out of the device. In the WRITE mode, data must
remain stable while SCL is HIGH. In the READ mode, data
is clocked out on the falling edge of SCL.
Serial Data (SDA)
- The SDA pin is a bidirectional pin
used to transfer data into and out of the device. Data may
change only when SCL is LOW, except START and STOP
conditions. It is an open-drain output and may be wire-
ORed with any number of open-drain or open-collector
outputs.
RESET# -
RESET# is an active low open-drain output. It
should be tied high through a pull-up resistor connected to
V
CC
. RESET# is an I/O, therefore it may also be used to
condition a RESET# signal generated by another device;
it can also be used to debounce a pushbutton input.
RESET -
RESET is an active high open drain (PFET)
output. It should be tied low through a pull-down resistor
connected to ground. RESET is an I/O, therefore it may
also be used to condition a RESET signal generated by
another device.
V
SENSE
- The V
SENSE
input is used as a second voltage
sensing input. The pin is tied to a comparator that uses the
precision internal 1.25V reference.
V
LOW
#
- V
LOW
# is an active low open drain output driven
low whenever V
SENSE
is below 1.25V. It is not a timed
output and only responds to the state of V
SENSE
.
ENDURANCE AND DATA RETENTION
The S42xxx is designed for applications requiring
100,000 erase/write cycles and unlimited read cycles. It
provides 100 years of secure data retention, with or
without power applied, after the execution of 100,000
erase/write cycles.
Reset Controller Description
The S42xxx provides a precision RESET controller that
ensures correct system operation during brown-out and
power-up/-down conditions. It is configured with two open
drain RESET outputs; pin 7 is an active high output and
pin 2 is an active low output. For proper operation pin 7
should be tied low through a pull-down resistor while pin
2 should be tied high through a resistor connected to V
CC
.
During power-up, the RESET outputs remain active until
V
CC
reaches the V
TRIP
threshold and will continue driving
the outputs for t
PURST
(200 msec)after reaching V
TRIP
.
The RESET outputs will be valid so long as V
CC
is > 1.0V.
During power-down, the RESET outputs will begin driving
active when V
CC
falls below V
TRIP
.
The RESET pins are I/Os; therefore, the S42xxx can act
as a signal conditioning circuit for an externally applied
reset. The inputs are edge triggered; that is, the RESET
input will initiate a reset timeout after detecting a low to
high transition and the RESET# input will initiate a reset
timeout after detecting a high to low transition. Refer to the
applications information section for more details on de-
vice operation as a reset conditioning circuit.
Voltage Sensor Description
V
SENSE
is an auxiliary voltage detection circuit. Its thresh-
old is set at 1.25V and it generates a V
LOW
# output for an
under-voltage condition. Because the V
LOW
# output is
open-drain, it can be wire-ORed with the RESET# output
or tied directly to an IRQ input on a microcontroller.
2025 6.0 4/17/00
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SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
