S4242/S42WD42/S4261/S42WD61
Random Address Byte Read
After the word address acknowledge is received by the
Random address read operations allow the master to master, the master immediately reissues a start condition
access any memory location in a random fashion. This followed by another slave address field with the R/W bit
operation involves a two-step process. First, the master set to READ. The S42xxx will respond with an acknowl-
issues a write command which includes the start condi- edge and then transmit the 8-data bits stored at the
tion and the slave address field (with the R/W bit set to addressed location. At this point, the master does not
WRITE) followed by the address of the word it is to read. acknowledgethetransmissionbutdoesgeneratethestop
This procedure sets the internal address counter of the condition. The S42xxx discontinues data transmission
S42xxx to the desired address.
and reverts to its standby power mode. See Figure 13 for
the address, acknowledge and data transfer sequence.
A
C
K
A
C
K
A
C
K
*
A
10 9
*
A
A
8
R
W
A
10
A
9
A
8
R
W
Word Address
Data Byte
SDA Bus
Activity
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1 0 1 0
0
1 0 1 0
1
1
S
T
A
R
T
S
T
A
R
T
S
T
O
P
Device
Device
Type
Address
A10,A9,A8
A10,A9,A8
Type
Address
Read/Write
0= Write
Read/Write
1= Read
Lack of ACK (low)
from Master
determines last
data byte to be read
Slave Address
Slave Address
Master sends Read
request to Slave
Master Writes Word
Address to Slave
Master Requests
Data from Slave
Slave sends
Data to Master
Master Transmitter
to
Master Transmitter
to
Master Transmitter
to
Slave Transmitter
to
Slave Receiver
Slave Receiver
Slave Receiver
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Shading Denotes
42xxx
SDA Output Active
2025 ILL13.1
* S4261/S42WD61 only
FIGURE 13. RANDOM ADDRESS BYTE READ MODE
2025 6.0 4/17/00
11
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
