USBUFxxW6
Figure 6.
USBUFxxW6 ESD clamping behavior
Rg
Technical information
S1
Rt
S2
Rd
V
PP
Vinput
Voutput
Rd
Rload
V
BR
V
BR
Device
to be
protected
ESD Surge
USBUF01W6
Figure 7.
ESD
SURGE
Measurement board
TEST BOARD
16kV
Air
Discharge
UUx
Vin
Vout
To have a good approximation of the remaining voltages at both Vin and Vout stages, we
give the typical dynamical resistance value Rd. By taking into account these following
hypothesis: R
t
> R
d
, R
g
> R
d
and R
load
> R
d
, it gives these formulas:
R
g
⋅
V
BR
+
R
d
⋅
V
g
Vinput
= ----------------------------------------------
-
R
g
R
t
⋅
V
BR
+
R
d
⋅
Vinput
V
ouput
= ------------------------------------------------------
-
R
t
The results of the calculation done for V
g
= 8 kV, R
g
= 330
Ω
(IEC 61000-4-2 standard),
V
BR
= 7 V (typ.) and R
d
= 1
Ω
(typ.) give:
Vinput = 31.2 V
Voutput = 7.95 V
This confirms the very low remaining voltage across the device to be protected. It is also
important to note that in this approximation the parasitic inductance effect was not taken into
account. This could be few tenths of volts during few ns at the V
input
side. This parasitic
effect is not present at the V
output
side due the low current involved after the resistance R
t
.
The measurements done hereafter show very clearly (figure 8) the high efficiency of the
ESD protection:
●
●
no influence of the parasitic inductances on Voutput stage
Voutput clamping voltage very close to V
BR
(breakdown voltage) in the positive way
and - V
F
(forward voltage) in the negative way
5/11
STMICROELECTRONICS [ STMICROELECTRONICS ]
